CXD1915R View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXD1915R

Digital Video Encoder

Sony Semiconductor 

CXD1915R

Pin Description

Pin

No.

Symbol

1 F1

2 XVRST

3 XIICEN

4 XCS/SA

5 SI/SDA

6 SO

7 VSS1

8 SCK/SCL

9 VSS2

10 SYSCLK

11 VSS3

12 XRST

13 VSS4

14 PDCLK

15 VDD1

16 FID

I/O

Description

Field ID input.

I

This signal indicates the field ID when resetting the vertical sync.

High indicates 1st field.

Low indicates 2nd field.

Vertical sync reset input in active Low. This pin is pulled up. This is used for

I synchronizing the phases of the external and internal vertical sync signals. When

XVRST = Low, the internal digital sync generator is reset according to the F1 status.

Serial interface mode select input. This pin is pulled up.

I When XIICEN = Low, Pins 4, 5, 6 and 8 are I2C bus mode.

When XIICEN = High, Pins 4, 5, 6 and 8 are Sony SIO mode.

This pin's function is selected by XIICEN (Pin 3). This pin is pulled up.

I

When XIICEN = High, this pin is Sony SIO mode; XCS chip select input.

When XIICEN = Low, this pin is I2C bus mode; SA slave address select input

signal which selects the I2C bus slave address.

This pin's function is selected by XIICEN (Pin 3).

I/O When XIICEN = High, this pin is Sony SIO mode; SI serial data input.

When XIICEN = Low, this pin is I2C bus mode; SDA input/output.

This pin's function is selected by XIICEN (Pin 3).

O When XIICEN = High, this pin is Sony SIO mode; SO serial output.

When XIICEN = Low, this pin is not used and output is high impedance.

— Digital ground.

This pin's function is selected by XIICEN (Pin 3).

I When XIICEN = High, this pin is Sony SIO mode; SCK serial clock input.

When XIICEN = Low, this pin is I2C bus mode; SCL input.

— Digital ground.

I

System clock input.

To generate the correct subcarrier frequency, precise 27MHz is required.

— Digital ground.

I

System reset input in active Low.

Set to Low for 40 clocks (SYSCLK) or more during power-on reset.

— Digital ground.

Pixel data clock signal output for 13.5MHz.

O A 13.5MHz signal frequency divided from the system clock (SYSCLK) is output

and used as the clock signal when 16-bit pixel data is input.

— Digital power supply.

Field ID input/output.

When SYNCM (Pin 72) = High, the CXD1915R is set to master mode and outputs

as follows.

When control register bit "FIDS" = "1":

I/O

Low indicates 1st field and High indicates 2nd field.

When control register bit "FIDS" = "0":

High indicates 1st field and Low indicates 2nd field.

When SYNCM (Pin 72) = Low, the CXD1915R is set to slave mode and this pin

becomes the field ID input.

–3–

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