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XD010-EVAL View Datasheet(PDF) - Sirenza Microdevices => RFMD

Part Name
Description
Manufacturer
XD010-EVAL
Sirenza
Sirenza Microdevices => RFMD Sirenza
XD010-EVAL Datasheet PDF : 3 Pages
1 2 3
XD010-EVAL Test Fixture
J3 - Pin Description
Pin # Function
Description
1
VG1
Gate control for stage 1. Sets the quiecent bias current on Pin 3 of the XD Module. Typical val-
ues 4.0 – 4.4Vdc. This pin is not used with D2 and D4 modules.
2
Gnd
DC ground for D package module. Also connected to RF ground.
3
VD1
Drain voltage for the first stage. Nominally +28Vdc.
4
Vx
Not used.
5
VG2
Gate control for stage 2. Sets the quiecent bias current on Pin 5. Typical values 4.0 – 4.4Vdc.
This pin is not used with D2 and D4 modules.
6
VD2
Drain voltage for the second stage. Nominally +28Vdc
Test Board Layout
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-103395 Rev D

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