DDP3310B View Datasheet(PDF) - Micronas

Part Name

Description

Manufacturer

DDP3310B

Display and Deflection Processor

Micronas 

ADVANCE INFORMATION

DDP 3310B

3. Serial Interface

3.1. I2C-Bus Interface

Communication between the DDP 3310B and the

external controller is done via I2C-bus. The

DDP 3310B has an I2C-bus slave interface and uses

I2C clock synchronization to slow down the interface if

required.

Basically, there are two classes of registers in the

DDP 3310B:

1. The first class are directly addressable I2C registers.

They are embedded in the hardware. These regis-

ters are 8 or 16 bit wide.

2. The second class are “XDFP-REGISTERS”, which

are used by the “XDFP” on-chip controller. These

registers are all 16 bit wide and read- and writable.

Communication with these registers requires I2C

packets with a 16-bit XDFP-register address and

16-bit data.

Communication with both classes of registers (I2C and

XDFP-REGISTERS) are performed via I2C; but the for-

mat of the I2C telegram depends on which type of reg-

ister is being accessed.

The I2C-bus chip address of the DDP 3310B is given

below:

A6 A5 A4 A3 A2 A1 A0 R/W

1 0 0 0 1 0 1 1/0

3.2. I2C Control and Status Registers

The I2C-bus interface uses one level of subaddress.

First, the bus address selects the IC, then a subad-

dress selects one of the internal registers. They have

8- or 16-bit data size; 16-bit registers are accessed by

reading/writing two 8-bit data words.

– Writing is done by sending the device address first

followed by the subaddress byte and one or two

data bytes.

– For reading, the read address has to be transmitted

first by sending the device write address, followed

by the subaddress, a second start condition with the

device read address, and reading one or two bytes

of data.

Fig. 3–2 shows I2C protocol for read and write opera-

tions; the read operation requires an extra start condi-

tion and repetition of the chip address with read com-

mand set. Table 3–2 gives definitions of the I2C control

and status registers.

SDA

1

S

SCL

0

P

S = I2C-Bus Start Condition

P = I2C-Bus Stop Condition

Fig. 3–1: I2C-Bus protocol (MSB first, data must be stable while clock is High)

Write to I2C Control Register :

S 1000 101 W Ack Sub-Addr. Ack 1- or 2-Byte Data Ack P

Read from I2C Control Register :

S 1000 101 W Ack Sub-Addr. Ack S

1000 101 R Ack High-Byte Data Ack Low-Byte Data Nak P

W = 0 (Write Bit)

R = 1 (Read Bit)

S = Start Condition

P = Stop Condition

Fig. 3–2: I2C-Bus protocol

Ack = 0 (Acknowledge Bit from DDP 3310B=gray

or controller=hatched)

Nak = 1 (Not Acknowledge Bit from controller=hatched

or indicating an error state from DDP 3310B=gray)

Micronas

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