YSS950 View Datasheet(PDF) - Yamaha Corporation
Part Name
Description
Manufacturer
YSS950 Datasheet PDF : 30 Pages
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YSS950
（2） Serial Data Interface
Serial data input
SDI7 to
SDI0
Transfer
format
control
Mute Channel
control control
DSP
Data
format
control
Serial data output
Bypass Channel
control control
Mute
control
Transfer
format
control
SDO 7 to
SDO 0
Bypass
[Note]
The following serial data interface control register (addresses 0x0E to 0x2A, except SD*MTN) and
ICHCNFG[1:0] (address 0x08) should be set in the software reset mode. If changes are required when in the
normal operation mode, perform the following steps to prevent abnormal sounds.
<1> Set mute (SD*MTN = 1→0, SD*MTSET = 1).
<2> Set the DSP mode to on-chip memory access burst transfer mode (DSPMOD = 1→0).
<3> Set serial data interface control register /ICHCNFG[1:0].
<4> Wait for at least 1024 samples.
<5> Set the DSP mode to signal processing mode (DSPMOD = 0→1).
<6> Cancel mute (SD*MTN = 0→1, SD*MTSET = 1).
(a) Interface clock control
Registers
SDIMCK
SDIBCK
SDIWCK
1/2
1/4
1/6
1/8
1/12
4
5
6
7
8
9
0
sel
0
1
2
3
4
5 sel
4
5
6
7
8
9
0
1/2
1
1/4
2
1/8
3
sel
1/64
1
1/128
2
1/256
3
0 sel
sdibck
Serial Data Input
1/64
1
1/128
2
1/256
3
0
sdiwck
sel
10
10
sel
sdobck
sel
sdowck
Serial Data Output
SDOMCK
SDOBCK
SDOWCK
15
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