Z89C00 View Datasheet(PDF) - Zilog
Part Name
Description
Manufacturer
Z89C00 Datasheet PDF : 28 Pages
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ZILOG
No.
1-9
10
11-26
27-38
39
40-43
44-46
47
48
49
50
51
52
53
54-55
56-58
59-60
61-64
65
66-68
PRELIMINARY
Table 1. 68-Pin PLCC Pin Identification
Symbol
Function
EXT15-EXT7
VSS
PD15-PD0
PA11-PA0
External data bus
Ground
Program data bus
Program address bus
V
DD
PA15-PA12
EA2-EA0
/EI
Power Supply
Program address bus
External address bus
R/W for external bus
ER//W
/RDYE
/RES
CLK
External bus direction
Data ready
Reset
Clock
/ROMEN
HALT
UI1-UI0
INT2-INT1
Enable ROM
Stop execution
User inputs
Interrupts
UO1-UO0
EXT3-EXT0
VSS
EXT6-EXT4
User outputs
External data bus
Ground
External data bus
Z89C00
16-BIT DIGITAL SIGNAL PROCESSOR
Direction
Input/Output
Input
Input
Output
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Output
Input/Output
Input
Input/Output
PIN FUNCTIONS
CLK Clock (input). External clock. The clock may be
stopped to reduce power.
EXT15-EXT0 External Data Bus (input/output). Data bus
for user defined outside registers such as an ADC or DAC.
The pins are normally in output mode except when the
outside registers are specified as source registers in the
instructions. All the control signals exist to allow a read or
a write through this bus.
ER//W External Bus Direction (output, active Low). Data
direction signal for EXT-Bus. Data is available from the
CPU on EXT15-EXT0 when this signal is Low. EXT-Bus is in
input mode (high-impedance) when this signal is High.
EA2-EA0 External Address (output). User-defined register
address output. One of eight user-defined external registers
is selected by the processor with these address pins for
read or write operations. Since the addresses are part of
the processor memory map, the processor is simply
executing internal reads and writes.
/EI Enable Input (output). Write timing signal for EXT-Bus.
Data is read by the external peripheral on the rising edge
of /EI. Data is read by the processor on the rising edge of
CLK, not /EI.
HALT Halt State (input). Stop Execution Control. The CPU
continuously executes NOPs and the program counter
remains at the same value when this pin is held High. This
signal must be synchronized with CLK.
INT2-INT0 Three Interrupts (rising edge triggered). Interrupt
request 2-0. Interrupts are generated on the rising edge of
the input signal. Interrupt vectors for the interrupt service
starting address are stored in the program memory locations
0FFFH for INT0, 0FFEH for INT1 and 0FFDH for INT2.
Priority is: 2 = lowest, 0 = highest.
PA15-PA0 Program memory address bus (output). For up
to 64K x 16 external program memory. These lines are tri-
stated during Reset Low.
4
DC 4083-00
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