Z89C00 View Datasheet(PDF) - Zilog
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Description
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Z89C00 Datasheet PDF : 28 Pages
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ZILOG
FUNCTIONAL DESCRIPTION
PRELIMINARY
Z89C00
16-BIT DIGITAL SIGNAL PROCESSOR
General. The Z89C00 is a high-performance Digital Signal
Processor with a modified Harvard-type architecture with
separate program and data memory. The design has been
optimized for processing power and minimizing silicon
space.
Instruction Timing. Many instructions are executed in one
machine cycle. Long immediate instructions and Jump or
Call instructions are executed in two machine cycles.
When the program memory is referenced in internal RAM
indirect mode, it takes three machine cycles. In addition,
one more machine cycle is required if the PC is selected as
the destination of a data transfer instruction. This only
happens in the case of a register indirect branch instruction.
An Acc + P => Acc; a(i) * b(j) → P calculation and
modification of the RAM pointers, is done in one machine
cycle. Both operands, a(i) and b(j), can be located in two
independent RAM (0 and 1) addresses.
ALU. The 24-bit ALU has two input ports, one of which is
connected to the output of the 24-bit Accumulator. The
other input is connected to the 24-bit P-Bus, the upper
16 bits of which are connected to the 16-bit D-Bus. A shifter
between the P-Bus and the ALU input port can shift the
data by three bits right, one bit right, one bit left or no shift.
Hardware Stack. A six-level hardware stack is connected
to the D-Bus to hold subroutine return addresses or data.
The CALL instruction pushes PC+2 onto the stack. The
RET instruction pops the contents of the stack to the PC.
User Inputs. The Z89C00 has two inputs, UI0 and UI1,
which may be used by jump and call instructions. The jump
or call tests one of these pins and if appropriate, jumps to
a new location. Otherwise, the instruction behaves like a
NOP. These inputs are also connected to the status register
bits S10 and S11 which may be read by the appropriate
instruction (Figure 3).
Multiply/Accumulate. The multiplier can perform a 16-bit
x 16-bit multiply or multiply accumulate in one machine
cycle using the Accumulator and/or both the X and Y
inputs. The multiplier produces a 32-bit result, however,
only the 24 most significant bits are saved for the next
instruction or accumulation. The multiplier provides a flow
through operation whenever the X or Y register is updated,
an automatic multiply operation is performed and the P
register is updated. For operations on very small numbers
where the least significant bits are important, the data
should first be scaled by eight bits (or the multiplier and
multiplicand by four bits each) to avoid truncation errors.
Note that all inputs to the multiplier should be fractional
two’s complement 16-bit binary numbers. This puts them
in the range [–1 to 0.9999695], and the result is in 24-bits
so that the range is [–1 to 0.9999999]. In addition, if 8000H
is loaded into both X and Y registers, the resulting
multiplication is considered an illegal operation as an
overflow would result. Positive one cannot be represented
in fractional notation, and the multiplier will actually yield
the result 8000H x 8000H = 8000H (–1 x –1 = –1).
User Outputs. The status register bits S5 and S6 connect
through an inverter to UO0 and UO1 pins and may be
written to by the appropriate instruction.
Interrupts. The Z89C00 has three positive edge triggered
interrupt inputs. An interrupt is acknowledged at the end of
any instruction execution. It takes two machine cycles to
enter an interrupt instruction sequence. The PC is pushed
onto the stack. A RET instruction transfers the contents
of the stack to the PC and decrements the stack pointer
by one word. The priority of the interrupts is 0 = highest,
2 = lowest.
Registers. The Z89C00 has 12 physical internal registers
and up to eight user-defined external registers. The EA2-
EA0 determines the address of the external registers. The
/EI, /RDYE, and ER//W signals are used to read or write
from the external registers.
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DC 4083-00
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