MC33410FTA View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC33410FTA Datasheet PDF : 27 Pages
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MC33410
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No.
Bit 10
Bit 9
Bit 8
Shift Register Length
Polynomial
0
0
0
0
2
1 + z–1 + z–2
1
0
0
1
3
1 + z–2 + z–3
2
0
1
0
4
1 + z–3 + z–4
3
0
1
1
5
1 + z–3 + z–5
4
1
0
0
6
1 + z–5 + z–6
5
1
0
1
7
1 + z–6 + z–7
6
1
1
0
9
1 + z–5 + z–9
7
1
1
1
10
1 + z–7 + z–10
Data Slicer/Clock Recovery
The data slicer will receive the low level digital signal from
the RF receiver section at Pin 38. The input signal to the data
slicer must be >200 mVpp. Hysteresis of 50 mV is internally
provided. The output of the data slicer will be same
waveform, but with an amplitude of 0 to VCC, and can be
observed at Pin 36 (MP1) if bits 7/5–4 are set to 10. The
output can be inverted by setting bit 5/19 = 1.
The clock recovery block will generate a phase locked
clock, equal to the CVSD data rate, from the incoming data,
as long as the Encoder Counter (bits 4/23–18) is set for that
data rate. The recovered clock can be observed at Pin 39
(MP2) if bits 7/7–6 are set to 00. The data from the clock
recovery block can be observed at Pin 36 if bits 7/5–4 are set
to 00. The clock recovery block may be bypassed by setting
bit 7/0 to 1. With this setting the data slicer output will go
directly to the descrambler, and the encoder clock will
replace the Clock Recovery Clock.
Tables 6 and 7 summarize the options available at MP1
and MP2 (Pins 36 and 39).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 6. MP1 Options (Pin 36)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Register 7
Bit 5
Bit 4
Function
0
0
Data from clock recovery block
0
1
Data Detect Output
1
0
Data Slicer Output
1
1
Hi–Z/ CD Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 7. MP2 Options (Pin 39)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Register 7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bit 7
Bit 6
Function
0
0
Output recovered clock
0
1
Input CVSD Decoder clock
1
X
Disabled (Hi–Z)
When MP1 is set to a Hi–Z condition, the pin is an input for
the CD (Carrier Detect) function, with an input impedance of
600 KΩ. See the section entitled Low Battery/Carrier Detect
for an explanation of this function.
Descrambler
The descrambler receives the scrambled data from the
clock recovery block (or the data slicer if bit 7/0 = 1), and
descrambles it to the original data as long as the selected
taps are the same as those in the transmitting scrambler (see
Table 5). The descrambler block is the same configuration as
the scrambler, and is self–synchronizing. The descrambler
can be bypassed with bit 7/1.
Data Detect Register/Status Output/Rx Data Register
The Data Detect register will continuously compare the
descrambled data it receives with the 16 or 24–bit code word
stored in the Tx Data Register (loaded through register 8).
Upon detecting a match, and after the code word passes
through the shift register, the following (16 or 24–bit) data
word will be stored into the Rx Data Register, and then loaded
into register 10 of the MPU Interface. At this time the Status
output at Pin 13, and bit 5/22, will go high. The external
microprocessor can then retrieve the data word by reading
register 10, at which time the Status pin and bit will go low.
Upon detection of a code word as described above, the
CVSD Decoder will be provided with 32, 40, or 48–bits of a
1010 pattern (idle channel) to minimize disturbances to the
audio. After the data word is loaded into register 10, the
CVSD Decoder resumes receiving data from the
descrambler. The audio is therefore interrupted with a low
level signal for a maximum of 48 clock cycles (0.75 mSec at
64 kHz).
The Data Detect register can be bypassed by setting bit
7/3 = 1.
CVSD Decoder/Decoder Clock/Idle Channel
The CVSD Decoder will provide the analog equivalent, at
Pin 35, of the digital data it receives from the descrambler, or
from the 1010 generator (idle channel generator). There is a
single pole filter at the Decoder output to reduce the clock
noise normally present on a CVSD analog output. The CVSD
Decoder is self synchronizing as long as the decoder clock
matches the data rate, and the Decoder has been set with
bits 3/16–15 according to Table 2.
The Decoder clock is provided from the Clock Recovery
block by setting bits 7/7–6 to 00 or 1X. The clock is internally
provided to the Decoder, and is available at Pin 39.
Alternately, a Decoder clock can be provided from an
14
MOTOROLA RF/IF DEVICE DATA
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