93AA86A View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
93AA86A Datasheet PDF : 26 Pages
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93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.5 ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
FIGURE 2-2:
ERAL TIMING
CS
CLK
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be ≥ 4.5V for proper operation of ERAL.
TCSL
CHECK STATUS
DI
1
0
0
1
0
X •••
X
HIGH-Z
DO
TSV
BUSY
TEC
TCZ
READY
HIGH-Z
2004 Microchip Technology Inc.
DS21797D-page 7
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