MC74HC107N View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC74HC107N Datasheet PDF : 5 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual J-K Flip-Flop with Reset
High–Performance Silicon–Gate CMOS
The MC74HC107 is identical in pinout to the LS107. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Each flip flops negative edge clocked and has an active–low asynchro-
nous reset.
The HC107 is identical in function to the HC73, but has a different pinout.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 92 FETs or 23 Equivalent Gates
LOGIC DIAGRAM
1
J1
12
CLOCK 1
4
K1
13
RESET 1
3
Q1
2
Q1
8
J2
9
CLOCK 2
11
K2
5
Q2
6
Q2
RESET 2
10
PIN 14 = VCC
PIN 7 = GND
MC74HC107
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
J1 1
Q1 2
Q1 3
K1 4
Q2 5
Q2 6
GND 7
14 VCC
13 RESET 1
12 CLOCK 1
11 K2
10 RESET 2
9 CLOCK 2
8 J2
FUNCTION TABLE
Inputs
Reset Clock J
L
XX
H
L
H
L
H
H
H
H
H
LX
H
HX
H
X
Outputs
KQQ
XLH
L No Change
HLH
LHL
H
Toggle
X No Change
X No Change
X No Change
10/95
© Motorola, Inc. 1995
1
REV 6
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