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SAK-XC2765X-104F80LAA View Datasheet(PDF) - Infineon Technologies

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Description
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SAK-XC2765X-104F80LAA Datasheet PDF : 63 Pages
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XC27x5X Derivatives
XC2000 Family / Base Line
Detailed Errata Description
INT_X.H004 SCU Interrupts Enabled After Reset
Following a reset, the SCU interrupts are enabled by default (register
SCU_INTDIS = 0000H). This may lead to interrupt requests being triggered in
the SCU immediately, even before user software has begun to execute. In the
SCU, multiple interrupt sources are `ORed` to a common interrupt node of the
CPU interrupt controller. Due to the “ORing” of multiple interrupt sources, only
one interrupt request to the interrupt controller will be generated if multiple
sources at the input of this OR gate are active at the same time. If user software
enables an interrupt in the interrupt controller (SCU_xIC) which shares the
same node as the SCU interrupt request active after reset, it may lead to the
effect of suppressing the intended interrupt source. So, for all SCU interrupt
sources which will not be used, make sure to disable the interrupt source
(SCU_INTDIS) and clear any pending request flags (SCU_xIC.IR) before
enabling interrupts in interrupt controller.
LXBUS_X.H001 Do Not Access Reserved Locations on the LXBus
Some of the on-chip peripherals are connected via the LXBus. The EBC
controls this access by using CS7 to define the LXBus area.
The memory map lists several sections occupied by the on-chip LXBus
peripherals MultiCAN and the USIC modules.
The reserved sections within the address range 20’0000H ... 20’FFFFH shown
in the memory map are designated to additional peripherals for future
derivatives. The sizes of the reserved sections depend on the chosen device
type.
These reserved sections must not be accessed by user software nor by
debuggers. Access to these sections may lead to a CPU lock situation caused
by a bus lock and also makes the software incompatible with other derivatives.
The error mode can only be left by a reset.
Errata Sheet
51
V1.5, 2013-02

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