CY8C4125FNI-483(T) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY8C4125FNI-483(T)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 4: PSoC 4100 Family

Datasheet

44-TQFP

Pin Name

24

P0.0

25

P0.1

26

P0.2

27

P0.3

28

P0.4

29

P0.5

30

P0.6

31

P0.7

32

XRES

33

VCCD

40-QFN

Pin Name

22

P0.0

23

P0.1

24

P0.2

25

P0.3

26

P0.4

27

P0.5

28

P0.6

29

P0.7

30

XRES

31

VCCD

28-SSOP

Pin Name

19

P0.0

20

P0.1

21

P0.2

22

P0.3

–

–

–

–

23

P0.6

24

P0.7

25 XRES

26 VCCD

48-TQFP

Pin Name

28

P0.0

29

P0.1

30

P0.2

31

P0.3

32

P0.4

33

P0.5

34

P0.6

35

P0.7

36

XRES

37

VCCD

Analog

comp1_inp

comp1_inn

comp2_inp

comp2_inn

–

–

–

–

–

–

–

–

–

–

–

–

38

VSSD

–

34

VDDD

32

VDDD 27

VDD

39

VDDD

–

35

VDDA

33

VDDA 27

VDD

40

VDDA

–

36

VSSA

34

VSSA 28

VSS

41

VSSA

–

37

P1.0

35

P1.0

1

P1.0

42

P1.0

ctb.oa0.inp

38

P1.1

36

P1.1

2

P1.1

43

P1.1

ctb.oa0.inm

39

P1.2

37

P1.2

3

P1.2

44

P1.2

ctb.oa0.out

40

P1.3

38

P1.3

–

–

45

P1.3

ctb.oa1.out

41

P1.4

39

P1.4

–

–

46

P1.4

ctb.oa1.inm

42

P1.5

–

–

–

–

47

P1.5

ctb.oa1.inp

43

P1.6

–

–

–

–

48

P1.6 ctb.oa0.inp_alt

44 P1.7/VREF 40 P1.7/VREF 4 P1.7/VREF 1 P1.7/VREF ctb.oa1.inp_alt

ext_vref

Alternate Functions for Pins

Alt 1

Alt 2

Alt 3

Alt 4

Pin Description

–

–

–

scb0_spi_ssel_1 Port 0 Pin 0: gpio, lcd, csd, scb0, comp

–

–

–

scb0_spi_ssel_2 Port 0 Pin 1: gpio, lcd, csd, scb0, comp

–

–

–

scb0_spi_ssel_3 Port 0 Pin 2: gpio, lcd, csd, scb0, comp

–

–

–

–

Port 0 Pin 3: gpio, lcd, csd, comp

–

scb1_uart_rx[1] scb1_i2c_scl[1] scb1_spi_mosi[1] Port 0 Pin 4: gpio, lcd, csd, scb1

–

scb1_uart_tx[1] scb1_i2c_sda[1] scb1_spi_miso[1] Port 0 Pin 5: gpio, lcd, csd, scb1

ext_clk

–

–

scb1_spi_clk[1] Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk

–

–

wakeup

scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1, wakeup

–

–

–

–

Chip reset, active low

–

–

–

–

Regulated supply, connect to 1µF cap or

1.8V

–

–

–

–

Digital Ground

–

–

–

–

Digital Supply, 1.8 - 5.5V

–

–

–

–

Analog Supply, 1.8 - 5.5V, equal to VDDD

–

–

–

–

Analog Ground

tcpwm2_p[1]

–

–

–

Port 1 Pin 0: gpio, lcd, csd, ctb, pwm

tcpwm2_n[1]

–

–

–

Port 1 Pin 1: gpio, lcd, csd, ctb, pwm

tcpwm3_p[1]

–

–

–

Port 1 Pin 2: gpio, lcd, csd, ctb, pwm

tcpwm3_n[1]

–

–

–

Port 1 Pin 3: gpio, lcd, csd, ctb, pwm

–

–

–

–

Port 1 Pin 4: gpio, lcd, csd, ctb

–

–

–

–

Port 1 Pin 5: gpio, lcd, csd, ctb

–

–

–

–

Port 1 Pin 6: gpio, lcd, csd

–

–

–

–

Port 1 Pin 7: gpio, lcd, csd, ext_ref

Notes:

1. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively.

2. P3.2 and P3.3 are SWD pins after boot (reset).

Document Number: 001-87220 Rev. *J

Page 10 of 43

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