STP16CP05PTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STP16CP05PTR Datasheet PDF : 30 Pages
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STP16CP05
Timing diagrams
5
Timing diagrams
Table 9: Truth table
CLOCK LE/DM1 OE/DM2 SERIAL-IN OUT0 ......... OUT7 ......... OUT15
SDO
_|¯
H
_|¯
L
_|¯
H
¯|_
X
¯|_
X
L
Dn
L
Dn + 1
L
Dn + 2
L
Dn + 3
H
Dn + 3
Dn ..... Dn - 7 ..... Dn -15
No change
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn + 2 ..... Dn - 5 ..... Dn -13
OFF
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7: Timing diagram
1 Latch and output enable terminals are level-sensitive and are not synchronized
with rising or falling edge of CLK signal.
2 When LE/DM1 terminal is low level, the latch circuit holds previous set of data.
3 When LE/DM1 terminal is high level, the latch circuit refreshes new set of data
from SDI chain.
4 When OE/DM2 terminal is at low level, the output terminals Out 0 to Out 15
respond to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF.
5 When OE/DM2 terminal is at high level, all output terminals are switched OFF.
DocID12568 Rev 13
11/30
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