CXD1961Q View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
Manufacturer
CXD1961Q Datasheet PDF : 15 Pages
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CXD1961Q
Functional Description
(1) CPU Interface
CXD1961Q has two CPU interface, an 8 bit CPU bus and an I2C bus interface. Fix CPUSEL (Pin 5) to DC L or
H level depending on the choice of bus.
CPUSEL=L : I2C bus / H : 8 bit bus
I2C bus Interface
The CXD1961Q's slave address is "1101110", and the read/write operation is based on Philips standard.
<Write Data>
In write operation, the second byte is input as the sub-address of the start position. The 3rd byte then forms
the data to be written to the start register.
Successive data bytes are written to successive sub-address register.
S Slave
A Sub-
T Address 0 C Address
A 1101110 K Nhex
A
A
A
Input data
Input data
C
C
C
for "N"
for "N+1"
K
K
K
•••
AS
CT
KP
STA : Start condition
ACK : Acknowledgment by CXD1961Q
STP : Stop Condition
Note)
Registers of Sub-Address 0hex to 3hex are read only
<Read Data>
Before read operation, the sub-address of the start register to be read is input by using write operation, and
terminated by a stop condition.
Read operation then begins with the second byte which is the data of the start register. Data of successive
sub-address registers are read successively following by the second byte.
S Slave
A Sub-
T Address 0 C Address
A 1101110 K Nhex
AS
CT
KP
S Slave
A
A
A
Output data Output data
T Address 1 C
C
C
from "N"
from "N+1"
A 1101110 K
K
K
•••
Note)
Registers of Sub-Address 4hex to Fhex are write only
AS
CT
KP
—9—
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