SAA4970T View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

SAA4970T

Economical video processing IC (ECOBENDIC)

Philips Electronics 

Philips Semiconductors

Economical video processing IC

(ECOBENDIC)

Preliminary specification

SAA4970T

VARIABLE INPUT AND OUTPUT DELAYS

To obtain flexibility, a programmable delay difference

between Y and UV can be made at both input and output.

At the input an almost symmetrical range of Y to UV delay

can be made: −3 to +4 clock pulses.

At the output a range of Y to UV delay from −5 to +2 clock

pulses can be made. When using e.g. scavenge circuitry,

which has an additional external delay, the lower delays in

Y are able to compensate this.

COLOUR REFORMATTING

The reformatter changes the DMSD 4 : 1 : 1 format UV

signals into a sequential 8-bit U and V format according to

the following scheme:

input:

U7, U5, U3, U1, U7, U5...etc.

U6, U4, U2, U0, U6, U4...etc.

V7, V5, V3, V1, V7, V5...etc.

V6, V4, V2, V0, V6, V4...etc.

output:

U7, V7, U7, V7...etc.

U6, V6, U6, V6...etc.

U5, V5, U5, V5...etc.

U4, V4, U4, V4...etc.

U3, V3, U3, V3...etc.

U2, V2, U2, V2...etc.

U1, V1, U1, V1...etc.

U0, V0, U0, V0...etc.

If the master clock frequency in the IC is 27 MHz then the

data rate of the reformatter output is 13.5 MHz.

The signals UVbin and UV8bit, supplied by the

microcontroller interface, select binary/twos complement

mode and 8-bit/7-bit operation.

Economy Controller - Programmable Signal

Positioner (ECO-PSP) control/microcontroller

interface and sync processing

The control/microcontroller interface and sync processing

part is designed as a separate unit called the ECO-PSP.

HORIZONTAL AND ACQUISITION BLOCK

CNT_A is an 8-bit counter, which counts up to

256 positions per acquisition video line. The cycle length

of the counter is determined by either:

an external reset (rising edge of R1) on every line or

an internal reset, generated at a certain value of the

counter itself.

For operation with the internal reset only, a value N in the

‘reset CNT_A’ register will result in an N + 1 length cycle.

The R1 signal, generated by the ECO-PLL, should then be

kept at a constant level. This however has not been

foreseen in the ECO-PLL, so this mode of operation is not

implied.

For operation with the external reset only, the ‘reset

CNT_A’ register must be loaded with a value above the

maximum line length. A value of FFH is suggested.

The VI1 input signal is monitored on its rising edge, with

regard to the CNT_A momentary value. By reading out

MUXA the positions of the edge becomes available for the

microcontroller. If VI1 is the video field pulse, the position

of the active edge within a video line becomes available.

This indicates the interlace situation of the acquisition

video signal. A window for discrimination of undesired VI1

edges is used. This window is made in the vertical

acquisition block.

If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXA will

be loaded with the momentary CNT_A contents.

The PIP input signal is monitored on its edges, with regard

to the CNT_A momentary values. If the PIP interrupt is

enabled, an occurring rising edge will generate acquisition

interrupt. By reading out MUXF and MUXG, the positions

of the rising and falling edges become available for the

microcontroller.

The internal acquisition gate pulses GA1, GA2 and GA3

(routed to CLMP, WE and IE) are set and reset at

selectable CNT_A values. The sets of GA2 and GA3 have

to be enabled by the vertical acquisition block. If the set

and reset registers have equal contents, the signal will

remain reset (reset overruling set).

The internal acquisition horizontal pulse HI is HIGH when

the CNT_A contents are equal to a programmable value in

the HI position register.

1996 Oct 25

11

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