AD7669 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7669

LC2MOS Complete, 8-Bit Analog I/0 Systems

Analog Devices 

AD7569/AD7669

PIN FUNCTION DESCRIPTION

(Applies to the AD7569 and AD7669 unless otherwise stated.)

Pin

Mnemonic

Description

Pin

Mnemonic

Description

AGNDDAC

Analog Ground for the DAC(s). Separate

ground return paths are provided for the

DAC(s) and ADC to minimize crosstalk.

VOUT

Output Voltage. VOUT is the buffered output

(VOUTA, VOUTB) voltage from the AD7569 DAC. VOUTA and

VOUTB are the buffered DAC output voltages

from the AD7669. Four different output volt-

age ranges can be achieved (see Table I).

VSS

RANGE

Negative Supply Voltage (–5 V for dual sup-

ply or 0 V for single supply). This pin is also

used with the RANGE pin to select the differ-

ent input/output ranges and changes the data

format from binary (VSS = 0 V) to 2s comple-

ment (VSS = –5 V) (see Table I).

Range Selection Input. This is used with the

VSS input to select the different ranges as per

Table I. The range selected applies to both

the analog input voltage of the ADC and the

output voltage from the DAC(s).

RESET

Reset Input (Active Low). This is an asyn-

chronous system reset that clears the DAC

register(s) to all 0s and clears the INT line of

the ADC (i.e., makes the ADC ready for new

conversion). In unipolar operation, this input

sets the output voltage to 0 V; in bipolar

operation, it sets the output to negative full

scale.

DB7

Data Bit 7. Most Significant Bit (MSB).

DB6–DB2

Data Bit 6 to Data Bit 2.

DGND

Digital Ground.

DB1

Data Bit 1.

DB0

Data Bit 0. Least Significant Bit (LSB).

WR

Write Input (Edge triggered). This is used in

conjunction with CS to write data into the

AD7569 DAC register. It is used in conjunc-

tion with CS and A/B to write data into the

selected DAC register of the AD7669. Data is

transferred on the rising edge of WR.

CS

RD

ST

BUSY

INT

A/B (AD7669

Only)

CLK

AGNDADC

VIN

VDD

Chip Select Input (Active Low). The device is

selected when this input is active.

READ Input (Active Low). This input must

be active to access data from the part. In the

Mode 2 interface, RD going low starts con-

version. It is used in conjunction with the CS

input (see Digital Interface Section).

Start Conversion (Edge triggered). This is

used when precise sampling is required. The

falling edge of ST starts conversion and drives

BUSY low. The ST signal is not gated with

CS.

BUSY Status Output (Active Low). When

this pin is active, the ADC is performing a

conversion. The input signal is held prior to

the falling edge of BUSY (see Digital Inter-

face Section).

INTERRUPT Output (Active Low). INT go-

ing low indicates that the conversion is com-

plete. INT goes high on the rising edge of CS

or RD and is also set high by a low pulse on

RESET (see Digital Interface Section).

DAC Select Input. This input selects which

DAC register data is written to under control

of CS and WR. With this input low, data is

written to the DACA register; with this input

high, data is written to the DACB register.

A TTL compatible clock signal may be used

to determine the ADC conversion time. Inter-

nal clock operation is achieved by connecting

a resistor and capacitor to ground.

Analog Ground for the ADC.

Analog Input. Various input ranges can be se-

lected (see Table I).

Positive Supply Voltage (+5 V).

Range

0

1

0

1

Table I. Input/Output Ranges

Input/Output

DB0–DB7

VSS

Voltage Range Data Format

0V

0 V to +1.25 V

Binary

0V

0 V to +2.5 V

Binary

–5 V

± 1.25 V

2s Complement

–5 V

± 2.5 V

2s Complement

REV. B

–7–

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