AD9801 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9801 Datasheet PDF : 12 Pages
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AD9801
APPLICATION INFORMATION
Generating Clock Signals
For best performance, the AD9801 should be driven by 3 V
1
14
logic levels. As shown in the Equivalent Input Circuits, the use
2
13
+3V
of 5 V logic for ADCCLK will turn on the protection diode to
DVDD, increasing the current flow into this pin. As a result,
noise and power dissipation will increase. The CDS clock inputs,
SHP and SHD, have additional protection and can withstand
direct 5 V levels.
+3V
PGACONT2
1µF
3
12
AD8402-10
4
11
5
10
6
9
0.1µF
PGACONT1
+3V
1µF
External clamping diodes or resistor dividers can be used to
7
8
translate 5 V levels to 3 V levels, but the lowest power dissipa-
SHDN CS
SDI CLK RS
tion is achieved with a logic transceiver chip. National Semi-
conductor’s 74LVX4245 provides a 5 V to 3 V level shift for up
Figure 21. Digital Control of PGA
OBSOLETE to eight clock signals, and features a three-state option and low
power consumption. Philips Semiconductor and Quality also
manufacture similar devices.
Digitally Programmable Gain Control
The AD9801’s PGA is controlled by an analog input voltage of
0.3 V to 2.7 V. In some applications, digital gain control is
preferable. Figure 21 shows a circuit using Analog Devices’
AD8402 Digital Potentiometer to generate the PGA control
voltage. The AD8402 functions as two individual potentiom-
eters, with a serial digital interface to program the position of
each wiper over 256 positions. The device will operate with 3 V
or 5 V supplies, and features a power-down mode and a reset
function.
To keep external components to a minimum, the ends of the
“potentiometers” can be tied to ground and +3 V. One pot is
used for the coarse gain adjust, PGACONT1, with steps of
about 0.2 dB/LSB. The other pot is used for fine gain control,
reference may be used. The REF193 from Analog Devices
features low power, low dropout performance, maintaining a
3 V output with a minimum 3.1 V supply when lightly loaded.
Power and Grounding Recommendations
The AD9801 should be treated as an analog component when
used in a system. The same power supply and ground plane
should be used for all of the pins. In a two-ground system, this
requires that the digital supply pins be decoupled to the analog
ground plane and the digital ground pins be connected to
analog ground for best noise performance. If any pins on the
AD9801 are connected to the system digital ground, noise can
capacitively couple inside the AD9801 (through package and die
parasitics) from the digital circuitry to the analog circuitry.
Separate digital supplies can be used, particularly if slightly
different driver supplies are needed, but the digital power pins
should still be decoupled to the same point as the digital ground
pins (analog ground plane). If the AD9801 digital outputs need
PGACONT2, and is capable of around 0.01 dB steps if all
to drive a bus or substantial load, a buffer should be used at the
eight bits are used. The two outputs should be filtered with 1 µF AD9801’s outputs, with the buffer referenced to system digital
or larger capacitors to minimize noise into the PGACONT pins ground. In some cases, when system digital noise is not
of the AD9801.
substantial, it is acceptable to split the ground pins on the
The disadvantage of this circuit is that the control voltage
will be supply dependent. If additional precision is required,
an external op amp can be used to amplify the VREFT (1.75 V)
AD9801 to separate analog and digital ground planes. If this is
done, be sure to connect the ground pins together at the
AD9801.
or VREFB (1.25 V) pins on the AD9801 to the desired voltage
level. These reference voltages are stable over the operating
supply range of the AD9801. Low power, low cost, rail-to-rail
output amplifiers such as the AD820, OP150 and OP196 are
specified for 3 V operation. Alternatively, a precision voltage
To further improve performance, isolating the driver supply
DRVDD from DVDD with a ferrite bead can help reduce
kickback effects during major code transitions. Alternatively,
the use of damping resistors on the digital outputs will reduce
the output risetimes, reducing the kickback effect.
–10–
REV. 0
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