AD9801 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9801 Datasheet PDF : 12 Pages
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AD9801
PIN CONFIGURATION
36 35 34 33 32 31 30 29 28 27 26 25
CMLEVEL 37
INT_BIAS2 38
24 DVSS
23 CLPDM
MODE2 39
22 SHD
MODE1 40
21 SHP
ADVSS 41
ADVDD 42
AD9801
20 CLPOB
19 PBLK
ADVDD 43
ADVSS 44
TOP VIEW
(Not to Scale)
18 STBY
17 DVDD
OBSOLETE ADVSS 45
SUBST 46
VRB 47
VRT 48
PIN 1
IDENTIFIER
16 ADCCLK
15 DVSS
14 DSUBST
13 DRVSS
1 2 3 4 5 6 7 8 9 10 11 12
Pin No. Pin Name
1
2–11
12
13
14
15
16
17
ADVSS
D0–D9
DRVDD
DRVSS
DSUBST
DVSS
ADCCLK
DVDD
Type
P
DO
P
P
P
P
DI
P
Description
Analog Ground
Digital Data Outputs
+3 V Digital Driver Supply
Digital Driver Ground
Digital Substrate
Digital Ground
ADC Sample Clock Input
+3 V Digital Supply
18
STBY
DI
Power down (Active HIGH)
19
PBLK
DI
Pixel Blanking (Active LOW)
20
CLPOB
DI
Black Level Restore Clamp (Active LOW)
21
SHP
DI
Reference Sample Clock Input
22
SHD
DI
Data Sample Clock Input
23
CLPDM
DI
Input Clamp (Active Low)
24
DVSS
DI
Digital Ground
25
CCDBYP2
AO
CCD Bypass (Decouple to Analog Ground Through 0.1 µF)
26
DIN
AI
CDS Input (Tie to Pin 27 and AC-Couple to CCD Output Through 0.1 µF)
27
PIN
AI
CDS Input (See Above)
28
CCDBYP1
AO
CCD Bypass (Decouple to Analog Ground Through 0.1 µF)
29
PGACONT1 AI
Coarse PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1 µF)
30
PGACONT2 AI
Fine PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1 µF)
31
ACVSS
P
Analog Ground
32
CLAMP_BIAS AO
Clamp Bias Level (Decouple to Analog Ground Through 0.1 µF)
33
ACVDD
P
+3 V Analog Supply
34
ACVDD
AI
+3 V Analog Supply
35
ACVDD
AI
+3 V Analog Supply
36
INT_BIAS1
AO
Internal Bias Level (Decouple to Analog Ground Through 0.1 µF)
37
CMLEVEL
AO
Common-Mode Level (Decouple to Analog Ground Through 0.1 µF)
38
INT_BIAS2
AO
Internal Bias Level (Decouple to Analog Ground Through 0.1 µF)
39
MODE2
DI
ADC Test Mode Control (See Digital Output Data Control)
40
MODE1
DI
ADC Test Mode Control (See Digital Output Data Control)
41
ADVSS
P
Analog Ground
42
ADVDD
P
+3 V Analog Supply
43
ADVDD
P
+3 V Analog Supply
44
ADVSS
P
Analog Ground
45
ADVSS
P
Analog Ground
46
SUBST
P
Substrate (Connect to Analog Ground)
47
VRB
AO
Bottom Reference Bypass (Decouple to Analog Ground Through 0.1 µF)
48
VRT
AO
Top Reference Bypass (Decouple to Analog Ground Through 0.1 µF)
–4–
REV. 0
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