ADIS16100ACC View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADIS16100ACC Datasheet PDF : 16 Pages
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ADIS16100
TIMING SPECIFICATIONS
TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1
Table 2.
Parameter
fSCLK 2
tCONVERT
tQUIET
t2
t3 3
t43
t5
t6
t7
t8 4
t9
t10
t11
VCC = VDRIVE = 5 V
10
20
16 × tSCLK
50
10
30
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
Description
Minimum quiet time required between CS rising edge and start of next conversion.
CS to SCLK setup time.
Delay from CS until DOUT three-state disabled.
Data access time after SCLK falling edge.
SCLK low pulse width.
SCLK high pulse width.
SCLK to DOUT valid hold time.
SCLK falling edge to DOUT high impedance.
DIN setup time prior to SCLK falling edge.
DIN hold time after SCLK falling edge.
16th SCLK falling edge to CS high.
1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans
from 4.75 V to 5.25 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. The time, t8, quoted in the Timing Specifications is the true bus relinquish time of the part
and is independent of the bus loading.
CS
t2
SCLK
tCONVERT
t6
1
2
3
4
5
6
t3
t4
t7
DOUT
ZERO ADD1 ADD0 DB11 DB10
THREE-STATE
ADDRESS BITS
ZERO t9
t10
DIN
WRITE LOW DONTC DONTC ADD1 ADD0
B
11
12
13
14
t5
DB4
DB3
DB2
DB1
15
16
t8
DB0
t11
tQUIET
THREE-STATE
CODING DONTC DONTC DONTC DONTC
Figure 2. Gyroscope Serial Interface Timing Diagram
200µA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 3. Load Circuit for Digital Output Timing Specifications
Rev. D | Page 5 of 16
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