ADM1021A(2012) View Datasheet(PDF) - ON Semiconductor
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Manufacturer
ADM1021A Datasheet PDF : 16 Pages
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ADM1021A
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(TA = TMIN to TMAX, VDD = 3.0 V to 3.6 V, unless otherwise noted) (Note 1)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SMBus Interface (See Figure 2)
Logic Input High Voltage, VIH
STBY, SCLK, SDATA
VDD = 3.0 V to 5.5 V
2.2
−
−
V
Logic Input Low Voltage, VIL
STBY, SCLK, SDATA
VDD = 3.0 V to 5.5 V
−
−
0.8
V
SMBus Output Low Sink Current
SDATA Forced to 0.6 V
6.0
−
−
mA
ALERT Output Low Sink Current
ALERT Forced to 0.4 V
1.0
−
−
mA
Logic Input Current, IIH, IIL
SMBus Input Capacitance, SCLK, SDATA
−1.0
−
+1.0
mA
−
5.0
−
pF
SMBus Clock Frequency
SMBus Clock Low Time, tLOW
SMBus Clock High Time, tHIGH
SMBus Start Condition Setup Time,
tSU:STA
SMBus Repeat Start Condition
tLOW between 10% Points
tHIGH between 90% Points
−
−
100
kHz
4.7
−
−
ms
4.0
−
−
ms
4.7
−
−
ms
250
−
−
ns
Setup Time, tSU:STA
Between 90% and 90% Points
250
−
SMBus Start Condition Hold Time, tHD:STA Time from 10% of SDATA to 90% of SCLK
4.0
−
SMBus Stop Condition Setup Time, tSU:STO Time from 90% of SCLK to 10% of SDATA
4.0
−
SMBus Data Valid to SCLK
Time for 10% or 90% of SDATA to 10% of SCLK
250
−
−
ns
−
ms
−
ms
−
ns
Rising Edge Time, tSU:DAT
SMBus Data Hold Time, tBUF:DAT
SMBus Bus Free Time, tBUF
SCLK Falling Edge to SDATA
Time for 10% or 90% of SDATA to 10% of SCLK
250
−
0
−
Between Start/Stop Condition
4.7
−
−
−
−
ns
−
ms
−
ms
1
ms
Valid Time, tVD:DAT
Master Clocking in Data
1. TMAX = 100C, TMIN = 0C
2. Operation at VDD = 5.0 V guaranteed by design; not production tested.
3. Guaranteed by design; not production tested.
−
−
1
ms
SCLK
SDATA
tBUF
STOP START
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
START
Figure 2. Serial Bus Timing
tSU; STO
STOP
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