Z80180 View Datasheet(PDF) - Zilog
Part Name
Description
Manufacturer
Z80180 Datasheet PDF : 70 Pages
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Zilog
φ
ADDRESS
IROQ
RD
WR
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
I/O Read Cycle
I/O Write Cycle
T1
T2
Tw
T3
T1
T2
Tw
T3
1
28
29
28
29
9
13
22
25
CPU Timing (IOC=0)
I/O Read Cycle
I/O Write Cycle
Figure 22. CPU Timing (/IOC = 0)
(I/O Read Cycle, I/O Write Cycle)
ø
/DREQi
(at level sense)
/DREQi
(at level sense)
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T1
T2
TW
T3
T1
45 46*1
*2
45 46
/TENDi
ST
47
*3 17
*4 18
48
1. tDRQS and tDHQH are specified for the rising edge of clock followed by T3.
*2. tDRQS and tDHQH are specified for the rising edge of clock.
*3. DMA cycle starts.
*4. CPU cycle starts
Figure 23. DMA Control Signals
DS971800401
PRELIMINARY
1-31
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