DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

ADV7123JST330(RevB) View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADV7123JST330
(Rev.:RevB)
ADI
Analog Devices ADI
ADV7123JST330 Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7123
3.3 V SPECIFICATIONS1 (VAA = 3.0 V–3.6 V, VREF = 1.235 V, RSET = 560 , CL = 10 pF. All specifications TMIN to TMAX2, unless
otherwise noted, TJ MAX = 110؇C.)
Parameter
Min Typ Max
Unit
Test Conditions2
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
–1
+0.5 +1
–1
+0.25 +1
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
2.0
0.8
–1
+1
20
Input Capacitance, CIN
10
ANALOG OUTPUTS
Output Current
DAC to DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
Gain Error3
2.0
26.5
2.0
18.5
1.0
0
1.4
70
10
0
0
0
Bits
LSB
LSB
V
V
µA
µA
pF
mA
mA
%
V
k
pF
% FSR
% FSR
RSET = 680
RSET = 680
RSET = 680
VIN = 0.0 V or VDD
Green DAC, Sync = High
RGB DAC, Sync = Low
Tested with DAC Output = 0 V
FSR = 17.62 mA
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
VOLTAGE REFERENCE (Int.)
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current4
Analog Supply Current
Standby Supply Current
Power Supply Rejection Ratio
1.12
1.235 1.35
1.235
2.2
5.0
6.5
12.0
11
15
16
67
72
8
2.1
5.0
0.1
0.5
V
V
mA
mA
mA
mA
mA
mA
mA
%/%
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
fCLK = 330 MHz
RSET = 560
RSET = 4933
PSAVE = Low, Digital, and Control
Inputs at VDD
NOTES
1These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
3Gain error = {(Measured (FSC)/Ideal (FSC) –1) × 100}, where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
4Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD.
Specifications subject to change without notice.
REV. B
–3–

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]