AT89LS8252-12PI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT89LS8252-12PI Datasheet PDF : 35 Pages
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Figure 9. SPI Transfer Format with CPHA = 1
SCK CYCLE #
(FOR REFERENCE)
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)
MSB
6
5
4
3
2
1
LSB
* MSB
6
5
4
3
2
1
LSB
*Not defined but normally LSB of previously transmitted character
Interrupts
The AT89LS8252 has a total of six interrupt vectors: two
external interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Note that Table 10 shows that bit position IE.6 is unimple-
mented. In the AT89C51 and AT89LV51, bit position IE.5 is
also unimplemented. User software should not write 1s to
these bit positions, since they may be used in future AT89
products.
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
Table 10. Interrupt Enable (IE) Register
(MSB)(LSB)
EA — ET2 ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Figure 10. Interrupt Sources
Symbol Position Function
Disables all interrupts. If EA = 0, no interrupt
EA
IE.7
is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.
—
IE.6 Reserved.
ET2
IE.5 Timer 2 interrupt enable bit.
ES
IE.4 SPI and UART interrupt enable bit.
ET1
IE.3 Timer 1 interrupt enable bit.
EX1
IE.2 External interrupt 1 enable bit.
ET0
IE.1 Timer 0 interrupt enable bit.
EX0
IE.0 External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.
16
AT89LS8252
0850C–MICRO–3/06
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