FX465 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
Manufacturer
FX465 Datasheet PDF : 9 Pages
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Pin Number
FX465 D5
1
VDD: Positive supply.
Function
2
Xtal/CIock: Input to the on-chip inverter; used with a 4.0MHz Xtal or external clock source.
3
Xtal: Output of the on-chip inverter (clock output).
4
Load/Latch: Controls 8 on-chip latches and is used to latch Rx/Tx, PTL, D - D . This pin is internally
05
pulled to VDD. A logic ‘1’ applied to this input puts the 8 latches into a 'transparent' mode. A logic ‘0’
applied to this input puts the 8 latches into the ‘latched’ mode.
In parallel mode data is loaded and latched by a logic ‘1’ to ‘0’ transition (see Figure 4).
In serial mode data is loaded and latched by a ‘0’ to ‘1’ to ‘0’ strobe pulse on this pin (see Figure 4).
5
D /Serial Enable: Data input D (Parallel Mode); Serial Enable (Serial Mode).
5
5
A logic ‘l’ applied to this input, together with a logic ‘0’ applied to D4/Serial Enable, will put the device
into 'Serial Mode' (see Figure 4). This pin is internally pulled to VDD.
6
D4/Serial Enable: Data input D4 (Parallel Mode); Serial Enable (Serial Mode).
A logic ‘0’ applied to this input, together with a logic ‘1’ applied to D5/Serial Enable, will place the device
into ‘Serial Mode’ (see Figure 4). This pin internally pulled to V .
DD
7
D3/Serial Data In: Data input D3 (Parallel Mode); Serial Data Input (Serial Mode).
In Serial Mode this pin becomes the serial data input for D5 - D0, Rx/Tx, PTL (see Figure 4). D5 is
clocked-in first and PTL last. This pin internally pulled to V .
DD
8
D2/Serial Clock: Data input D2 (Parallel Mode); Serial Clock Input (Serial Mode).
In Serial Mode this pin becomes the Serial Clock input. Data is clocked on the positive-going edge (see
Figure 4). This pin is internally pulled to VDD.
9
D1: Data input D1 (Parallel Mode); Not used (Serial Mode). This pin is internally pulled to VDD.
10
D : Data input D (Parallel Mode); Not used (Serial Mode). This pin is internally pulled to V .
0
0
DD
11
VSS: Negative supply.
12
Decode Comparator
the logical state of the
RRexfT. o(In/Pe):DeInctoedrneaplliyn.bRiaxseTdontoeVDDeD/c3odoer 2=VlDoDg/3ic
via
‘1’
1.0MΩ resistors depending
will bias this input to 2VDD/3,
on
a
logic ‘0’ will bias this input to VDD/3. This input provides the decode comparator reference voltage;
switching of bias voltages provides hysteresis to reduce 'chatter' under marginal conditions.
2
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