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Q67060-S7005-A2 View Datasheet(PDF) - Siemens AG

Part Name
Description
Manufacturer
Q67060-S7005-A2
Siemens
Siemens AG Siemens
Q67060-S7005-A2 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
BTS720L1
Truth Table
Channel 1 and 2
Chip 1
IN1 IN2 OUT1 OUT2
ST1/2
Channel 3 and 4
Chip 2
IN3 IN4 OUT3 OUT4
ST3/4
(equivalent to channel 1 and 2)
BTS 720L1
BTS 721L1
Normal operation
L
L
L
L
H
L
H
L
H
H
H
L
H
L
H
Open load
H
H
H
Channel 1 (3) L
L
Z
H
H
L
H(L13))
L
H
Z
H
H
H
X
H
Channel 2 (4) L
L
L
H
L
H
X
L
Z
H(L13))
Z
H
Short circuit to Vbb
X
H
X
Channel 1 (3) L
L
H
L
H
H
H
X
H
Channel 2 (4) L
L
L
H
L
L
L14)
H
H
X
H(L15))
H
L14)
H
L
H
X
H
X
H
H
H
H(L15))
Overtemperature
both channel
L
L
L
L
H
X
H
L
L
L
H
X
L
L
L
Channel 1 (3) L
X
L
X
H
H
X
L
X
L
Channel 2 (4) X
L
X
L
H
X
H
X
L
L
Undervoltage/ Overvoltage
X
X
L
L
H
L = "Low" Level
X = don't care
Z = high impedance, potential depends on external circuit
H = "High" Level
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
Ibb
Vbb
I IN1
I IN2
I ST1/2
VIN1 VIN2 VST1/2
3 IN1
Leadframe
VON1
VON2
Vbb
18
I L1
OUT1
5
IN2
PROFET
Chip 1
4 ST1/2 GND1/2
2
OUT2 17
I L2
VOUT1
IGND1/2
VOUT2
R GND1/2
I IN3
I IN4
I ST3/4
VIN3 VIN4 VST3/4
7 IN3
Leadframe
VON3
VON4
Vbb
14
I L3
OUT3
9
IN4
PROFET
Chip 2
8
ST3/4 GND3/4
6
OUT4 13
I L4
VOUT3
IGND3/4
VOUT4
R GND3/4
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20
External RGND optional; two resistors RGND1/2 ,RGND3/4 = 150 or a single resistor RGND = 75 for
reverse battery protection up to the max. operating voltage.
13) With additional external pull up resistor
14) An external short of output to Vbb in the off state causes an internal current from output to ground. If RGND is
used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
15) Low resistance to Vbb may be detected by no-load-detection
Semiconductor Group
Page 7
26.Feb.96

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