CD22357A View Datasheet(PDF) - Harris Semiconductor
Part Name
Description
Manufacturer
CD22357A Datasheet PDF : 10 Pages
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CD22354A, CD22357A
A rising edge on the receive frame sync, FSR, will cause the
PCM data at DR to be latched in on the next falling edge of the
BCLKR. The remaining seven bits are latched on the succes-
sive seven falling edges of the bit-clock (BCLKX in synchronous
mode).
Transmit Section
The transmit section consists of a gain-adjustable input op-
amp, an anti-aliasing filter, a low-pass filter, a high-pass filter
and a compressing A/D converter. The input op-amp drives a
RC active anti-aliasing filter. This filter eliminates the need for
any off-chip filtering as it provides 30dB attenuation (Min) at the
sampling frequency. From this filter the signal enters a 5th order
low-pass filter clocked at 128kHz, followed by a 3rd order high-
pass filter clock at 32kHz. The output of the high-pass filter directly
drives the encoder capacitor ladder at an 8kHz sampling rate. A
precision voltage reference is trimmed in manufacturing to provide
an input overload of nominally 2.5VPEAK. Transmit frame sync
pulse FSX controls the process. The 8-bit PCM data is clocked
out at DX by the BCLKX. BCLKX can be varied from 64kHz to
2.048MHz.
Receive Section
The receive section consists of an expanding D/A converter and a
low-pass filter which fulfills both the AT&T D3/D4 specifications
and CCITT recommendations. PCM data enters the receive sec-
tion at DR upon the occurrence of FSR, Receive Frame sync
pulse. BCLKR, Receive Data Clock, which can range from 64kHz
to 2.048MHz, clocks the 8-bit PCM data into the receive data reg-
ister. A D/A conversion is performed on the 8-bit PCM data and
the corresponding analog signal is held on the D/A capacitor lad-
der. This signal is transferred to a switched capacitor low-pass fil-
ter clocked at 128kHz to smooth the sample-and-hold signal as
well as to compensate for the (SIN X)/X distortion.
The filter is then followed by a second order Sallen and Key active
filter capable of driving a 600Ω load to a level of 7.2dBm.
TS X
MCLK R
MCLK X
t RM t FM
t WWH
BCLKX
t HOLD
FSX
t SF
DX
tHOLD
BCLKR
tSF
FSR
DR
t XDB
t WWL
t PM
t DZC
t SBFM
1
2
3
4
5
6
7
8
t HF
t DBD
1
tHF
1
2
2
3
3
4
4
5
5
6
6
t DZC
7
8
7
8
tSDB
tHDB
tHBD
1
2
3
4
5
6
7
8
FIGURE 1. SHORT FRAME-SYNC TIMING
4-173
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