CXD9450-24 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

CXD9450-24

Single-Chip FaxEngine Product Family

Unspecified 

Single-Chip FaxEngine Product Family

Single-Chip FaxEngine and Integrated Analog Device

Digital Telephone Answering Machine (DTAM)

(Optional)

The DTAM option provides digital answering machine

functionality by providing a low bit rate voice codec that

provides 24 minutes of voice storage per 4 Mbits of

memory.

Speakerphone (Optional)

The speakerphone option adds duplex digital

speakerphone capability for hands-free applications. An

additional Integrated Analog (IA) device is required for

microphone and speaker interface to support duplex

digital speakerphone operation.

Evaluation System (SCE100-ES)

The SCE100-ES Evaluation System provides

demonstration, prototype development, and evaluation

capabilities to facsimile machine developers using the

device set. In addition, it provides a plug-on board for the

operator panel, sockets for programmable parts, and

connectors for an emulator. The operator panel on the

Evaluation System allows for complete control and

monitoring of functions. All necessary sockets for

memory components are included. Jumper options and

test points are provided throughout the SCE100-ES

board.

The Evaluation System is the most convenient

environment for the developer needing to experiment

with the various interfaces encountered in a fax machine.

The Evaluation System, along with the hardware and

application code, comprises a working facsimile

machine.

Hardware Description

Integrated Controller (SCC)

The Controller contains an internal MC24 Processor with

a 16-MB address space and dedicated circuitry

optimized for facsimile image processing and monitoring

and for thermal or thermal transfer printer support.

The CPU provides fast instruction (up to 10 MHz clock

speed) execution and memory efficient input/output bit

manipulation. The CPU connects to other internal

functions over an 8-bit data bus and 24-bit address bus

and dedicated control lines.

The 24-bit external address bus, 8-bit data bus, control,

status, and decoded chip select signals support

connection to external ROM, SRAM, DRAM, and FLASH

memory.

DRAM Controller

The CXD9450 includes a DRAM controller with single and

page mode access support which supports fast, normal,

or slow refresh time. DRAM memory space is divided

into two blocks, up to 4 MB each. A maximum of 8 MB of

DRAM is supported. Each block has a programmable

size and starting address. Refresh is performed

automatically and is supported in Sleep and Stand-by

modes. CAS and RAS signal support is provided for two-

DRAM banks for both 4-bit and 8-bit organizations.

Access speeds from 50 ns to 70 ns can be supported.

The DRAM controller provides battery backup refresh

using DRAM battery power.

Software Development Tools

DMA Channels

The MC24 Software Development Kit (SDK) (McFERE2,

2500AD MC24 Macro Assembler, Linker, and Librarian)

is available to support software/firmware development.

This package can operate under the MS-DOS, Microsoft

Windows 3.x, and Windows 9x Operating Systems. This

versatility provides the developer with extensive tools for

code modifications and debugging.

Six internal DMA channels support memory access for

scanner, T.4/T.6, and resolution conversion. DMA

Channel 2 can be reprogrammed for external access to

thermal printing, thermal transfer, or plain paper inkjet

printing.

External RAM and ROM

Moveable and programmable size external SRAM

memory of up to 1 MB, DRAM memory of up to 8 MB,

and ROM of up to 2 MB can be directly connected to the

CXD9450. By using an external address decoder, the size

of SRAM and/or ROM can be extended. The ROM stores

all the program object code. SRAM is used by the

Embedded CPU for shading RAM, image line buffer

RAM, and ECM buffer.

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Conexant

100544C

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