CY2071AFI(2002) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY2071AFI
(Rev.:2002)
(Rev.:2002)
Cypress Semiconductor
CY2071AFI Datasheet PDF : 8 Pages
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CY2071A
Electrical Characteristics, Industrial 5.0V VDD =5.0V ±10%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min.
VOH
HIGH-Level Output Voltage IOH = –4.0 mA
2.4
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
VIH
HIGH-Level Input Voltage[6] Except Crystal Pins
2.0
VIL
LOW-Level Output Voltage[6] Except Crystal Pins
IIH
Input HIGH Current
VIN = VDD – 0.5V
IIL
Input LOW Current
VIN = 0.5V
IOZ
Output Leakage Current
Three State Outputs
IDD
VDD Supply Current[7]
VDD = VDD max. 5V operation, CL = 25 pF
Typ.
40
Max. Unit
V
0.4
V
V
0.8
V
10
µA
150 µA
250 µA
75 mA
Electrical Characteristics, Industrial 3.3V VDD =3.3V ±10%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min.
VOH
HIGH-Level Output Voltage IOH = –4.0 mA
2.4
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
VIH
HIGH-Level Input Voltage[6] Except Crystal Pins
2.0
VIL
LOW-Level Output Voltage[6] Except Crystal Pins
IIH
Input HIGH Current
VIN = VDD – 0.5V
IIL
Input LOW Current
VIN = 0.5V
IOZ
Output Leakage Current
Three State Outputs
IDD
VDD Supply Current[7]
VDD = VDD max. 3.3V operation, CL = 15 pF
Typ.
24
Max. Unit
V
0.4
V
V
0.8
V
10
µA
150 µA
250 µA
50 mA
Switching Characteristics, Commercial 5.0V[8]
Parameter
Name
Description
Min.
Typ.
Max.
t1
Output Period
Clock output range
CY2071A
7.692
5V operation
[130 MHz]
25-pF load
CY2071AF
10
[100 MHz]
2000
[500 kHz]
2000
[500 kHz]
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
0.8
1
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz ≤ fOUT ≤ 50 MHz)
350
500
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
250
350
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
45%
50%
55%
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
40%
50%
60%
t3
Rise Time[9]
Output clock rise time
1.5
2.5
t4
Fall Time[9]
Output clock fall time
1.5
2.5
t5
Skew
Skew delay between any two outputs with
0.5
identical frequencies (generated by the PLL)
Notes:
8. Guaranteed by design, not 100% tested.
9. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF.
10. Reference Output duty cycle depends on XTALIN duty cycle.
11. Measured at 1.4V.
Unit
ns
ns
%
ps
ps
ns
ns
ns
Document #: 38-07139 Rev. *A
Page 4 of 8
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