CY2071AI(2002) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY2071AI
(Rev.:2002)
(Rev.:2002)
Cypress Semiconductor
CY2071AI Datasheet PDF : 8 Pages
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CY2071A
Switching Characteristics, Commercial 3.3V[8]
Parameter
Name
Description
t1
Output Period
Clock output range
CY2071AS
3.3V operation
15-pF load
CY2071AF
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz ≤ fOUT ≤ 50 MHz)
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
t3
Rise Time[9]
Output clock rise time
t4
Fall Time[9]
Output clock fall time
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
Min.
10
[100 MHz]
12.50
[80 MHz]
45%
40%
Typ.
0.8
350
250
50%
50%
1.5
1.5
Max.
Unit
2000
ns
[500 kHz]
2000
ns
[500 kHz]
1
%
500
ps
350
ps
55%
60%
2.5
ns
2.5
ns
0.5
ns
Switching Characteristics, Industrial 5.0V[8]
Parameter
Name
Description
t1
Output Period
Clock output range
CY2071AI
5.0V operation
25-pF load
CY2071AFI
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz ≤ fOUT ≤ 50 MHz)
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
Min.
10
[100 MHz]
11.1
[90 MHz]
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
t3
Rise time[9]
Output clock rise time
t4
Fall time[9]
Output clock fall time
45%
40%
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
Typ.
0.8
350
250
50%
50%
1.5
1.5
Max.
Unit
2000
ns
[500 kHz]
2000
ns
[500 kHz]
1
%
500
ps
350
ps
55%
60%
2.5
ns
2.5
ns
0.5
ns
Document #: 38-07139 Rev. *A
Page 5 of 8
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