CY2071A View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY2071A Datasheet PDF : 9 Pages
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CY2071A
Electrical Characteristics, Industrial 5.0V: VDD = 5.0V ±10%, TA = –40°C to 85°C[8]
Parameter
Description
Conditions
Min.
VOH
HIGH-Level Output Voltage
IOH = –4.0 mA
2.4
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
VIH
HIGH-Level Input Voltage[9]
Except Crystal Pins
2.0
VIL
LOW-Level Output Voltage[9] Except Crystal Pins
IIH
Input HIGH Current
VIN = VDD – 0.5V
IIL
Input LOW Current
VIN = 0.5V
IOZ
Output Leakage Current
Three State Outputs
IDD
VDD Supply Current[10]
VDD = VDD max. 5V operation, CL = 25 pF
Typ.
40
Max. Unit
V
0.4 V
V
0.8 V
10 µA
150 µA
250 µA
75 mA
Electrical Characteristics, Industrial 3.3V VDD =3.3V ±10%, TA = –40°C to +85°C[8]
Parameter
Description
Conditions
Min.
VOH
HIGH-Level Output Voltage IOH = –4.0 mA
2.4
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
VIH
HIGH-Level Input Voltage[9] Except Crystal Pins
2.0
VIL
LOW-Level Output Voltage[9] Except Crystal Pins
IIH
Input HIGH Current
VIN = VDD – 0.5V
IIL
Input LOW Current
VIN = 0.5V
IOZ
Output Leakage Current
Three State Outputs
IDD
VDD Supply Current[10]
VDD = VDD max. 3.3V operation, CL = 15 pF
Typ. Max. Unit
V
0.4 V
V
0.8 V
10 µA
150 µA
250 µA
24
50 mA
Switching Characteristics, Commercial 5.0V[11]
Parameter
Name
t1
Output Period
Description
Clock output range 5V CY2071A
operation 25-pF load
CY2071AF
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz ≤ fOUT ≤ 50 MHz)
t1C
Clock Jitter[12]
Peak-to-peak period jitter (fOUT > 50 MHz)
Output Duty Cycle
Duty cycle[13, 14] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
Output Duty Cycle[12] Duty cycle[14] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
t3
Rise Time[12]
Output clock rise time
t4
Fall Time[12]
Output clock fall time
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
Min.
7.692
[130 MHz]
10
[100 MHz]
45%
40%
Typ.
0.8
Max. Unit
2000
ns
[500 kHz]
2000
ns
[500 kHz]
1
%
350
500
ps
250
350
ps
50%
55%
50%
60%
1.5
2.5
ns
1.5
2.5
ns
0.5
ns
Notes:
11. Guaranteed by design, not 100% tested.
12. When the output clock frequency is between 100 MHz and 130 MHz at 5V, the maximum capacitive load for these measurements is 15 pF.
13. Reference Output duty cycle depends on XTALIN duty cycle.
14. Measured at 1.4V.
Document #: 38-07139 Rev. *D
Page 4 of 9
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