CY2071AFI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY2071AFI Datasheet PDF : 9 Pages
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CY2071A
Switching Characteristics, Commercial 3.3V[11]
Parameter
Name
t1
Output Period
Description
Clock output range 3.3V operation CY2071AS
15-pF load
CY2071AF
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.), % of
clock period, fOUT ≤ 16 MHz
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz ≤ fOUT ≤ 50 MHz)
t1C
Clock Jitter[12]
Peak-to-peak period jitter (fOUT > 50 MHz)
Output Duty Cycle Duty cycle[13, 14] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
Output Duty
Cycle[12]
Duty cycle[14] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
t3
Rise Time[12]
Output clock rise time
t4
Fall Time[12]
Output clock fall time
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
Min.
10
[100 MHz]
12.50
[80 MHz]
45%
40%
Typ.
0.8
350
250
50%
50%
1.5
1.5
Max.
2000
[500 kHz]
2000
[500 kHz]
1
Unit
ns
ns
%
500
ps
350
ps
55%
60%
2.5
ns
2.5
ns
0.5
ns
Switching Characteristics, Industrial 5.0V[11]
Parameter
Name
t1
Output Period
Description
Clock output range 5.0V operation CY2071AI
25-pF load
CY2071AFI
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. –
t1 min.),
% of clock period, fOUT ≤ 16 MHz
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz ≤ fOUT ≤ 50 MHz)
t1C
Clock Jitter[12]
Peak-to-peak period jitter
(fOUT > 50 MHz)
Output Duty Cycle Duty cycle[13, 14] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
Output Duty
Cycle[12]
Duty cycle[14] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
t3
Rise time[12]
Output clock rise time
t4
Fall time[12]
Output clock fall time
t5
Skew
Skew delay between any two
outputs with identical frequencies
(generated by the PLL)
Min.
10
[100 MHz]
11.1
[90 MHz]
45%
40%
Typ.
0.8
350
250
50%
50%
1.5
1.5
Max. Unit
2000
ns
[500 kHz]
2000
ns
[500 kHz]
1
%
500
ps
350
ps
55%
60%
2.5
ns
2.5
ns
0.5
ns
Document #: 38-07139 Rev. *D
Page 5 of 9
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