CY2071AFI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY2071AFI Datasheet PDF : 9 Pages
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CY2071A
Switching Characteristics, Industrial 3.3V[11]
Parameter
Name
t1
Output Period
t1A
Clock Jitter
t1B
Clock Jitter
t1C
Clock Jitter[12]
Output Duty Cycle
Output Duty Cy-
cle[12]
t3
Rise time[12]
t4
Fall time[12]
t5
Skew
Description
Clock output range 3.3V operation CY2071AI
15-pF load
CY2071AFI
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
Peak-to-peak period jitter
(16 MHz ≤ fOUT ≤ 50 MHz)
Peak-to-peak period jitter (fOUT > 50 MHz)
Duty cycle[13, 14] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
Duty cycle[14] for outputs, (t2 ÷ t1), fOUT > 60 MHz
Output clock rise time
Output clock fall time
Skew delay between any two outputs with identi-
cal frequencies (generated by the PLL)
Min.
12.50
[80 MHz]
15.0
[66.6 MHz]
45%
40%
Typ.
0.8
350
250
50%
50%
1.5
1.5
Max. Unit
2000
ns
[500 kHz]
2000
ns
[500 kHz]
1
%
500
ps
350
ps
55%
60%
2.5
ns
2.5
ns
0.5
ns
Switching Waveforms
Figure 1. All Outputs Duty Cycle and Rise/Fall Time
t1
t2
2.4V
2.4V
VDD
OUTPUT
0.4V
0.4V
0V
t3
t4
Figure 2. Output-Output Clock Skew
OUTPUT
OUTPUT
t5
Test Circuit
VDD
0.1 µF
7
OUTPUTS
2
CLK output
CLOAD
Document #: 38-07139 Rev. *D
GND
Page 6 of 9
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