F25L004A View Datasheet(PDF) - [Elite Semiconductor Memory Technology Inc.
Part Name
Description
Manufacturer
F25L004A Datasheet PDF : 30 Pages
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ESMT
F25L004A
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the F25L004A. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, or Chip-Erase
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE . Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first
TABLE 5: DEVICE OPERATION INSTRUCTIONS
Cycle Type/
Operation1,2
Read
High-Speed-Read
Sector-Erase4,5 (4K Byte)
Block-Erase5 (64K Byte)
Chip-Erase5
Byte-Program5
Auto-Address-Increment-word
programming (AAI)6
Read-Status-Register
(RDSR)
Enable-Write-Status-Register
(EWSR)8
Write-Status-Register
(WRSR)8
Max
Freq
33 MHz
1
2
SIN
03H
0BH
SOUT SIN
Hi-Z A23-A16
Hi-Z A23-A16
SOUT
Hi-Z
Hi-Z
20H Hi-Z A23-A16 Hi-Z
D8H Hi-Z A23-A16 Hi-Z
60H
C7H
Hi-Z
-
-
02H Hi-Z A23-A16 Hi-Z
Bus Cycle
3
4
SIN SOUT SIN SOUT
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
-
-
-
-
A15-A8 Hi-Z A7-A0 Hi-Z
5
SIN SOUT
X DOUT
XX
--
--
--
DIN Hi-Z
6
SIN SOUT
X DOUT
--
--
--
--
ADH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z
05H Hi-Z X DOUT - Note7 - Note7 - Note7 - -
50MHz
50H Hi-Z -
-
-
- - - - - --
01H Hi-Z Data Hi-Z -
- -. - - - - -
Write-Enable (WREN) 11
06H Hi-Z -
-
-
- - - - - --
Write-Disable (WRDI)
04H Hi-Z -
-
-
- - - - - --
Read-Electronic-Signature9
(RES)
100MHz
ABH Hi-Z
X
12H
-
-
-
- - - --
Jedec-Read-ID (JEDEC-ID) 10
9FH Hi-Z X 8CH X 20H X 13H - - - -
Read-ID (RDID)
Enable SO to output RY/BY#
Status during AAI (EBSY)
Disable SO to output RY/BY#
Status during AAI (DBSY)
90H
8CH
12H
(A0=0)
90H
Hi-Z A23-A16
Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
X
12H
X
8CH
(A0=1)
70H Hi-Z -
-
-
- - ---
80H Hi-Z -
-
-
- - ---
1. Operation: SIN = Serial In, SOUT = Serial Out
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
3. One bus cycle is eight clock periods.
4. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
5. Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.6
7/30
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