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UPD61P24CS View Datasheet(PDF) - NEC => Renesas Technology

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Description
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UPD61P24CS Datasheet PDF : 36 Pages
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µPD61P24
11. PIN FUNCTIONS
11.1 KI/O Pin (P0)
This is the 8-bit I/O pin for key-scan output. When the control register (P1) is set for the input port, the port can
be used as an 8-bit input pin. When the port is set for the input mode, all of these pins are pulled down to the VSS
level inside the LSI.
At reset (all cleared), the value of I/O mode and output latch becomes undefined.
Figure 11-1. KI/O Pin Organization
(P1 )
P10
P00
Control register
P0
KI/O7
KI/O6
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
11.2 KI/O Pull-Down Resistor Configuration
Input/output selection
Output signal
Input signal
CMOS
V DD
P-ch
Pin
N-ch
V SS
R Pull-down resistor
N-ch
When KI/O is set to the input mode, pull-down resistor R is turned on.
9

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