HSP50216 View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

HSP50216

Four-Channel Programmable Digital Downconverter

Intersil 

HSP50216

Backend Data Routing

PATH 0

AGC

LOOP

FILTER

MUX

MAG: I

dphi/dt: Q

I1

Q1

GAIN

FROM

CIC

(4:0)

M

FILTER

U

COMPUTE

X

ENGINE

PATH 1

FIFO/

TIMER

PATH 2

AGC

MULT

CART

TO

POLAR

DESTINATION BIT MAP

(BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD)

EXT AGC

GAIN

SHIFT

d/dt

x1, x2

x4, x8

MAG

M

U

PHASE

X

I2

Q2

28 27 26 25 24 23 22 21 20 19 18

28

27

26, 25

24

23

22:18

AGC LOOP GAIN SELECT (PATH 01 ONLY)

UPDATE AGC LOOP (PATH 01 ONLY)

PATH 00 - - IMMEDIATE FILTER PROCESSOR FEEDBACK PATH

01 - - FIFO/AGC PATH

10 - - DIRECT OUT/CASCADE PATH

11 - - BOTH 00 AND 10 PATHS (FOR TEST)

STROBE OUTPUT SECTION (START SERIAL OUTPUT WITH THIS SAMPLE)

FEED MAG/PHASE BACK TO FILTER PROCESSOR

FILTER PROCESSOR SEQUENCE STEP NUMBER

A CIC filter has a gain of RN, where R is the decimation factor

and N is the number of stages. Because the CIC filter gain

can become very large with decimation, an attenuator is

provided ahead of the CIC to prevent overflow. The 24 bits of

sample data are placed on the low 24 bits of a 69 bit bus

(width of the first CIC integrator) for a gain of 2-45. A 32 bit

barrel shifter then provides a gain of 20 to 231 inclusive

before passing the data onto the CIC. The overall gain in the

pre-CIC attenuator can therefore be programmed to be any

one of 32 values from 2-45 to 2-14, inclusive (see IWA=*004,

bits 18:14). This shift factor is adjusted to keep the total

barrel shifter and CIC filter between 0.5 and 1.0. The

equation which should be used to compute the necessary

shift factor is:

Shift Factor = 45 - Ceiling(log2(RN)).

NOTE: With a CIC order of zero, the CIC shifter does not have

sufficient range to route more than 10 bits to the back end since the

maximum gain is 2-14 (the least significant 14 bits are lost).

Back End Section

One back-end processing section is provided per channel.

Each back end section consists of a filter compute engine, a

FIFO/timer for evenly spacing samples (important when

implementing interpolation filters and resamplers), an AGC

and a cartesian-to-polar coordinate conversion block. A

block diagram showing the major functional blocks and data

routing is shown above. The data input to the back end

section is through the filter compute engine. There are two

other inputs to the filter compute engine, they are a data

recirculation path for cascading filters and a magnitude and

dφ/dt feedback path for AM and FM filtering. There are seven

outputs from each back end processing section. These are I

and Q directly out of the filter compute engine (I2, Q2), I and

Q passed through the FIFO and AGC multipliers (I1, Q1),

magnitude (MAG), phase (or dφ/dt), and the AGC gain

control value (GAIN). The I2/Q2 outputs are used when

cascading back end stages. The routing of signals within the

back end processing section is controlled by the filter

compute engine. The routing information is embedded in the

instruction bit fields used to define the digital filter being

implemented in the filter compute engine.

11

FN4557.6

August 17, 2007

Share Link: