HMS97C8032 View Datasheet(PDF) - Hynix Semiconductor
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HMS97C8032 Datasheet PDF : 157 Pages
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HMS91C8032/97C8032
3.11 Machine Cycles
A machine cycle consists of a sequence of 6 states, numbered S1
through S6. One machine cycle period vary according to the SC-
MOD register value. Refer to Figure 3-6
Each state is divided into a Phase 1 half and a Phase 2 half. State
Sequence in HMS9XC8032 Devices shows that fetch/execute se-
quences in states and phases for various kinds of instructions.
Normally two program fetches are generated during each ma-
chine cycle, even if the instruction being executed doesn't require
it. If the instruction being executed doesn't need more code bytes,
the CPU simply ignores the extra fetch, and the Program Counter
is not incremented.
Execution of a one-cycle instruction (Figure 3-6) begins during
State 1 of the machine cycle, when the opcode is latched into the
Instruction Register. A second fetch occurs during S4 of the same
machine cycle. Execution is complete at the end of State 6 of this
machine cycle.
Osc.
C(XPTUACLl2o)ck
(fCPU)
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
P1 P2 P1P2 P1P2 P1 P2 P1P2 P1P2 P1 P2 P1P2 P1P2 P1P2 P1 P2 P1P2 P1P2
Read opcode.
Read next
opcode
(discard).
S1 S2 S3 S4 S5 S6
a. 1-byte, 1-cycle instruction, e.g., INC A
Read next opcode again.
Read opcode.
Read 2nd byte. Read next opcode.
S1 S2 S3 S4 S5 S6
b. 2-byte, 1-cycle Instruction, e.g., ADD A, #data
Read opcode.
Read next
opcode (discard)
Read next opcode again.
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
c. 1-byte, 2-cycle instruction, e.g., INC DPTR
Figure 3-6 State Sequence in HMS9XC8032 Devices
16
NOV., 2001 Ver 1.02
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