ISP1181 View Datasheet(PDF) - Philips Electronics
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ISP1181 Datasheet PDF : 69 Pages
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Philips Semiconductors
ISP1181
Full-speed USB interface
9.2 Endpoint FIFO size
The size of the FIFO determines the maximum packet size that the hardware can
support for a given endpoint. Only enabled endpoints are allocated space in the
shared FIFO storage, disabled endpoints have zero bytes. Table 5 lists the
programmable FIFO sizes.
The following bits in the Endpoint Configuration Register (ECR) affect FIFO
allocation:
• endpoint enable bit (FIFOEN)
• size bits of an enabled endpoint (FFOSZ[3:0])
• isochronous bit of an enabled endpoint (FFOISO).
Remark: Register changes that affect the allocation of the shared FIFO storage
among endpoints must not be made while valid data is present in any FIFO of the
enabled endpoints. Such changes will render all FIFO contents undefined.
Table 5: Programmable FIFO size
FFOSZ[3:0]
Non-isochronous
0000
8 bytes
0001
16 bytes
0010
32 bytes
0011
64 bytes
0100
reserved
0101
reserved
0110
reserved
0111
reserved
1000
interrupt IN 8 bytes,
rate feedback mode
1001
interrupt IN 16 bytes,
rate feedback mode
1010
interrupt IN 32 bytes,
rate feedback mode
1011
interrupt IN 64 bytes,
rate feedback mode
1100
reserved
1101
reserved
1110
reserved
1111
reserved
Isochronous
16 bytes
32 bytes
48 bytes
64 bytes
96 bytes
128 bytes
160 bytes
192 bytes
256 bytes
320 bytes
384 bytes
512 bytes
640 bytes
768 bytes
896 bytes
1023 bytes
Each programmable FIFO can be configured independently via its ECR, but the total
physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes
(512 bytes for non-isochronous FIFOs).
Table 6 shows an example of a configuration fitting in the maximum available space of
2462 bytes. The total number of logical bytes in the example is 1311. The physical
storage capacity used for double buffering is managed by the device hardware and is
transparent to the user.
9397 750 06896
Objective specification
Rev. 01 — 13 March 2000
© Philips Electronics N.V. 2000. All rights reserved.
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