KBY00U00VA-B450 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

KBY00U00VA-B450

8Gb DDP (512M x16) NAND Flash + 4Gb (64M x32 + 64M x32) 2/CS,2CKE DDP Mobile DDR SDRAM

Samsung 

KBY00U00VA-B450

datasheet

Rev. 1.0

MCP Memory

VCC

VSS

A13 - A30*

A0 - A12

X-Buffers

Latches

& Decoders

Y-Buffers

Latches

& Decoders

4,096M + 128M Bit for 4Gb

8,192M + 256M Bit for 8Gb DDP

NAND Flash

ARRAY

Data Register & S/A

Y-Gating

Command

CE

RE

WE

Command

Register

Control Logic

& High Voltage

Generator

I/O Buffers & Latches

Global Buffers

Output

Driver

CLE ALE WP

[Figure 1] Functional Block Diagram

VCC

VSS

I/0 0

I/0 7

1 Block = 64 Pages

(256K + 8K) Byte

2,048 blocks for 4Gb

4,096 blocks for 8Gb DDP

4K Bytes

128 Bytes

1 Page = (4K + 128)Bytes

1 Block = (4K + 128)Byte x 64 Pages

= (256K + 8K) Bytes

1 Device = (4K+128)B x 64Pages x 2,048 Blocks

= 4,224 Mbits for 4Gb

8 bit 1 Device = (4K+128)B x 64Pages x 4,096 Blocks

= 8,448 Mbits for 8Gb DDP

Page Register

4K Bytes

I/O 0 ~ I/O 7

128 Bytes

[Figure 2] Array Organization

[Table 1] Array address (x8)

I/O 0

I/O 1

1st Cycle

A0

A1

2nd Cycle

A8

A9

3rd Cycle

A13

A14

4th Cycle

A21

A22

5th Cycle

A29

*A30

I/O 2

A2

A10

A15

A23

*L

I/O 3

A3

A11

A16

A24

*L

I/O 4

A4

A12

A17

A25

*L

NOTE :

Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

* A30 is Row address for 8G DDP.

In case of 4G Mono, A30 must be set to "Low"

I/O 5

A5

*L

A18

A26

*L

I/O 6

A6

*L

A19

A27

*L

I/O 7

A7

*L

A20

A28

*L

Address

Column Address

Column Address

Row Address

Row Address

Row Address

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