KBY00U00VA-B450 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

KBY00U00VA-B450

8Gb DDP (512M x16) NAND Flash + 4Gb (64M x32 + 64M x32) 2/CS,2CKE DDP Mobile DDR SDRAM

Samsung 

KBY00U00VA-B450

datasheet

Rev. 1.0

MCP Memory

1. FEATURES

<Common>

• Operating Temperature : -25°C ~ 85°C

• Package : 137 FBGA Type - 10.5mmx13mmx1.2mmt, 0.8mm pitch

<NAND Flash>

• Voltage Supply

- 1.8V Device : 1.7V ~ 1.95V

• Organization

- Memory Cell Array :

(256M + 8M) x 16bit for 4Gb

(512M + 16M) x 16bit for 8Gb DDP

- Data Register : (2K + 64) x 16bit

• Automatic Program and Erase

- Page Program : (2K + 64)Word

- Block Erase : (128K + 4K)Word

• Page Read Operation

- Page Size : (2K + 64)Word

- Random Read : 60μs(Max.) (TBD)

- Serial Access : 42ns(Min.)

• Fast Write Cycle Time

- Page Program time : 420μs(Typ.) (TBD)

- Block Erase Time : 3ms(Typ.) (TBD)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

-Endurance : TBD Program/Erase Cycles

with 4bit/256Word ECC for x16

• Command Driven Operation

• Unique ID for Copyright Protection

<Mobile DDR>

• VDD/VDDQ = 1.8V/1.8V

• Double-data-rate architecture; two data transfers per clock cycle.

• Bidirectional data strobe (DQS).

• Four banks operation.

• Differential clock inputs (CK and CK).

• MRS cycle with address key programs.

- CAS Latency (3)

- Burst Length (2, 4, 8, 16)

- Burst Type (Sequential & Interleave)

• EMRS cycle with address key programs.

- Partial Array Self Refresh (Full, 1/2, 1/4 Array)

- Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8)

• Internal Temperature Compensated Self Refresh.

• All inputs except data & DM are sampled at the positive going edge of the

system clock (CK).

• Data I/O transactions on both edges of data strobe, DM for masking.

• Edge aligned data output, center aligned data input.

• No DLL; CK to DQS is not synchronized.

• DM for write masking only.

• Auto refresh duty cycle.

- 7.8us

• Clock stop capability

• 2/CS, 2CKE

Operating Frequency

Speed @CL31)

NOTE :

1) CAS Latency

DDR400

200MHz

Address configuration

Organization /CS CKE

64Mx32

CS0 CKE0

64Mx32

CS1 CKE1

Bank

BA0,BA1

BA0,BA1

Row

A0 - A13

A0 - A13

Column

A0 - A9

A0 - A9

- DM is internally loaded to match DQ and DQS identically.

-3-

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