LC7455 View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC7455

Closed Caption Signal Extraction IC

SANYO -> Panasonic 

System Block Diagram

LC7455A, 7455M

PLL reference clock

mode 2

mode 3, 4

mode 1

Data peak hold

(Data slice)

Pedestal clamp

Hsync peak hold

(Hsync slice)

Output control

Divided-by-

32 circuit

(Modes 1, 3, 4)

Oscillator

circuit

(Mode 2)

(Mode 2)

Data output

buffer

Operation in the Different Modes

Pin

MOD1 MOD0

Open Open

Open

VDD

VDD

VDD

Open

VDD

Mode Application

equipment

Operation

Mode 1 VCR

Mode 2 VCR

Mode 3 NTSC-TV

Mode 4 PAL-TV

· Even field line 21 data extraction

The internal PLL is operated with the horizontal synchronizing signal separated from the composite video

signal as the reference.

· Even field line 21 data extraction

An external 508 kHz ceramic oscillator is used, and the internal PLL is operated with that oscillator output

divided by 32 as the reference.

· Odd and even field line 21 data extraction

The internal PLL is operated with the Hsync signal applied from fly back as the reference.

· Odd and even field line 22 data extraction

The internal PLL is operated with the Hsync signal applied from the fly back circuit as the reference.

Note: The data extraction operations in modes 1 and 2 are identical. However, while mode 1 can operate without problem for normal "on air" signals, it may

be difficult for the PLL to lock with signals such as scrambled CATV signals.

No. 5680-3/13

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