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LPC2104FBD48/01 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
Manufacturer
LPC2104FBD48/01 Datasheet PDF : 41 Pages
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NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table 3. Pin description …continued
Symbol
Pin
Type
P0.11/CTS1/CAP1.1 36[1]
I/O
I
I
P0.12/DSR1/MAT1.0 37[1]
I/O
I
O
P0.13/DTR1/MAT1.1 41[1]
I/O
O
O
P0.14/DCD1/EINT1 44[1]
I/O
I
I
P0.15/RI1/EINT2
45[1]
I/O
I
O
P0.16/EINT0/MAT0.2 46[1]
I/O
I
O
P0.17/CAP1.2/TRST 47[1]
I/O
I
I
P0.18/CAP1.3/TMS 48[1]
I/O
I
I
P0.19/MAT1.2/TCK 1[1]
I/O
O
I
P0.20/MAT1.3/TDI 2[1]
I/O
O
I
P0.21/PWM5/TDO 3[1]
I/O
O
O
P0.22/TRACECLK
32[4]
I/O
O
P0.23/PIPESTAT0
33[4]
I/O
O
P0.24/PIPESTAT1
34[4]
I/O
O
P0.25/PIPESTAT2
38[4]
I/O
O
Description
P0.11 — Port 0 bit 11.
CTS1 — Clear to Send input for UART 1.
CAP1.1 — Capture input for Timer 1, channel 1.
P0.12 — Port 0 bit 12.
DSR1 — Data Set Ready input for UART 1.
MAT1.0 — Match output for Timer 1, channel 0.
P0.13 — Port 0 bit 13.
DTR1 — Data Terminal Ready output for UART 1.
MAT1.1 — Match output for Timer 1, channel 1.
P0.14 — Port 0 bit 14.
DCD1 — Data Carrier Detect input for UART 1.
EINT1 — External interrupt 1 input.
P0.15 — Port 0 bit 15.
RI1 — Ring Indicator input for UART 1.
EINT2 — External interrupt 2 input.
P0.16 — Port 0 bit 16.
EINT0 — External interrupt 0 input.
MAT0.2 — Match output for Timer 0, channel 2.
P0.17 — Port 0 bit 17.
CAP1.2 — Capture input for Timer 1, channel 2.
TRST — Test Reset for JTAG interface, primary JTAG pin group.
P0.18 — Port 0 bit 18.
CAP1.3 — Capture input for Timer 1, channel 3.
TMS — Test Mode Select for JTAG interface, primary JTAG pin group.
P0.19 — Port 0 bit 19.
MAT1.2 — Match output for Timer 1, channel 2.
TCK — Test Clock for JTAG interface, primary JTAG pin group.
P0.20 — Port 0 bit 20.
MAT1.3 — Match output for Timer 1, channel 3.
TDI — Test Data In for JTAG interface, primary JTAG pin group.
P0.21 — Port 0 bit 21.
PWM5 — Pulse Width Modulator output 5.
TDO — Test Data Out for JTAG interface, primary JTAG pin group.
P0.22 — Port 0 bit 22.
TRACECLK — Trace Clock. Standard I/O port with internal pull-up.
P0.23 — Port 0 bit 23.
PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P0.24 — Port 0 bit 24.
PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P0.25 — Port 0 bit 25.
PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.
LPC2104_2105_2106_7
Product data sheet
Rev. 07 — 20 June 2008
© NXP B.V. 2008. All rights reserved.
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