LPC2104FBD48/01 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC2104FBD48/01

Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM

NXP Semiconductors. 

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Table 3. Pin description …continued

Symbol

Pin

Type

P0.26/TRACESYNC 39[4]

I/O

O

P0.27/TRACEPKT0/ 8[4]

I/O

TRST

O

I

P0.28/TRACEPKT1/ 9[4]

I/O

TMS

O

I

P0.29/TRACEPKT2/ 10[4]

I/O

TCK

O

I

P0.30/TRACEPKT3/ 15[4]

I/O

TDI

O

I

P0.31/EXTIN0/TDO 16[4]

I/O

I

O

RTCK

26[4]

I/O

DBGSEL

RESET

XTAL1

XTAL2

VSS

VDD(1V8)

VDD(3V3)

n.c.

27

I

6[5]

I

11

I

12

O

7, 19, I

31, 43

5

I

17, 40 I

4, 20, -

25, 42

Description

P0.26 — Port 0 bit 26.

TRACESYNC — Trace Synchronization Standard I/O port with internal pull-up.

P0.27 — Port 0 bit 27.

TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

TRST — Test Reset for JTAG interface, secondary JTAG pin group.

P0.28 — Port 0 bit 28.

TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

TMS — Test Mode Select for JTAG interface, secondary JTAG pin group.

P0.29 — Port 0 bit 29.

TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

TCK — Test Clock for JTAG interface, secondary JTAG pin group. This clock

must be slower than 1/6 of the CPU clock (CCLK) for the JTAG interface to

operate.

P0.30 — Port 0 bit 30.

TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

TDI — Test Data In for JTAG interface, secondary JTAG pin group.

P0.31 — Port 0 bit 31.

EXTIN0 — External Trigger Input. Standard I/O port with internal pull-up.

TDO — Test Data out for JTAG interface, secondary JTAG pin group.

Returned Test Clock output: Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Also used during

debug mode entry to select primary or secondary JTAG pins with the 48-pin

package. Bidirectional pin with internal pull-up.

Debug Select: When LOW, the part operates normally. When HIGH, debug

mode is entered. Input pin with internal pull-down.

external reset input; a LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

input to the oscillator circuit and internal clock generator circuits.

output from the oscillator amplifier.

ground: 0 V reference.

1.8 V core power supply; this is the power supply voltage for internal circuitry.

3.3 V pad power supply; this is the power supply voltage for the I/O ports.

not connected; these pins are not connected in the 48-pin package.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires external pull-up to provide an output

functionality. Open-drain configuration applies to all functions on this pin.

[3] SSP interface available on LPC2104/2105/2106/01 only.

[4] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.

[5] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

© NXP B.V. 2008. All rights reserved.

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