LTC4263CDE View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC4263CDE

14-Bit, 65Msps ADC

Linear Technology 

LTC2205-14

APPLICATIONS INFORMATION

CONVERTER OPERATION

The LTC2205-14 is a CMOS pipelined multi-step converter

with a front-end PGA. As shown in Figure 1, the converter

has five pipelined ADC stages; a sampled analog input

will result in a digitized value seven cycles later (see the

Timing Diagram section). The analog input is differential for

improved common mode noise immunity and to maximize

the input range. Additionally, the differential input drive

will reduce even order harmonics of the sample and hold

circuit. The encode input is also differential for improved

common mode noise immunity.

The LTC2205-14 has two phases of operation, determined

by the state of the differential ENC+/ENC– input pins. For

brevity, the text will refer to ENC+ greater than ENC– as

ENC high and ENC+ less than ENC– as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC, a

reconstruction DAC and a residue amplifier. In operation,

the ADC quantizes the input to the stage, and the quantized

value is subtracted from the input by the DAC to produce a

residue. The residue is amplified and output by the residue

amplifier. Successive stages operate out of phase so that

when odd stages are outputting their residue, the even

stages are acquiring that residue and vice versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the voltage on the

sample capacitors is held. While ENC is high, the held

input voltage is buffered by the S/H amplifier which drives

the first pipelined ADC stage. The first stage acquires

the output of the S/H amplifier during the high phase of

ENC. When ENC goes back low, the first stage produces

its residue which is acquired by the second stage. At

the same time, the input S/H goes back to acquiring the

analog input. When ENC goes high, the second stage

produces its residue which is acquired by the third stage.

An identical process is repeated for the third and fourth

stages, resulting in a fourth stage residue that is sent to

the fifth stage for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally delayed such that

the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2205-14

CMOS differential sample and hold. The differential analog

inputs are sampled directly onto sampling capacitors

(CSAMPLE) through NMOS transitors. The capacitors shown

attached to each input (CPARASITIC) are the summation of

all other capacitance associated with each input.

During the sample phase when ENC is low, the NMOS

transistors connect the analog inputs to the sampling

capacitors which charge to, and track the differential

input voltage. When ENC transitions from low to high, the

sampled input voltage is held on the sampling capacitors.

LTC2005-14

VDD

AIN+

VDD

AIN–

RPARASITIC

3Ω

RPARASITIC

3Ω

VDD

CPARASITIC

1.8pF

CPARASITIC

1.8pF

RON

CSAMPLE

4.9pF

20Ω

RON

CSAMPLE

4.9pF

20Ω

ENC+

ENC–

1.6V

6k

6k

1.6V

Figure 2. Equivalent Input Circuit

220514 F02

220514fb

15

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