M2S56D20AKP View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
M2S56D20AKP Datasheet PDF : 41 Pages
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DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
M2S56D20/ 30/ 40AKT
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
CLK, /CLK
CKE
/CS
/RAS, /CAS, /WE
A0-12
TYPE
Input
Input
Input
Input
Input
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh.After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
DQS
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Input / Output Data Input/Output: Data bus
Input / Output
Data Strobe: Output pin during Read operation, input pin during Write
operation. Edge-aligned with read data, placed at the centered of write data
to capture the write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with the input data
DM
Input
during a WRITE operations. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
VDD, VSS Power Supply Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ Power Supply VDDQ and VSSQ are supplied to the Output Buffers only.
VREF
Input
SSTL_2 reference voltage.
5
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