M2S28D20ATP View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M2S28D20ATP

128M Double Data Rate Synchronous DRAM

Mitsumi 

DDR SDRAM (Rev.0.1)

Jun,'00 Preliminary

MITSUBISHI LSIs

M2S28D20/ 30/ 40ATP

128M Double Data Rate Synchronous DRAM

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a

SDRAM from damaged or multifunctioning.

1. Apply VDD before or the same time as VDDQ

2. Apply VDDQ before or at the same time as VTT & Vref

3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL

4. Issue precharge command for all banks of the device

5. Issue EMRS

6. Issue MRS for the Mode Register and to reset the DLL

7. Issue 2 or more Auto Refresh commands

8. Maintain stable condition for 200 cycle

After these sequence, the DDR SDRAM is idle state and ready for normal operation.

MODE REGISTER

CLK

Burst Length, Burst Type and /CAS Latency can be

/CLK

programmed by setting the mode register (MRS). The mode

/CS

register stores these data until the next MRS command, which

may be issued when both banks are in idle state. After tRSC from

/RAS

a MRS command, the DDR SDRAM is ready for new command.

/CAS

/WE

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0

BA1

0 0 0 0 0 DR 0 LTMODE BT

BL

A11-A0

V

Latency

Mode

CL

000

001

010

011

100

101

110

111

/CAS Latency

R

R

2

R

R

R

2.5

R

0

NO

DLL Reset

1

YES

Burst

Length

BL

000

001

010

011

100

101

110

111

BT=0

R

2

4

8

R

R

R

R

BT=1

R

2

4

8

R

R

R

R

0

Burst Type

1

Sequential

Interleaved

R: Reserved for Future Use

MITSUBISHI ELECTRIC

13

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