M34282MX-XXXGP View Datasheet(PDF) - Renesas Electronics
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Description
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M34282MX-XXXGP Datasheet PDF : 69 Pages
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4282 Group
RAM BACK-UP MODE
The 4282 Group has the RAM back-up mode.
When the POF instruction is executed, system enters the RAM
back-up state.
As oscillation stops retaining RAM, the functions and states of
reset circuit at RAM back-up mode, power dissipation can be
reduced without losing the contents of RAM. Table 7 shows the
function and states retained at RAM back-up. Figure 23 shows
the state transition.
(1) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF
instruction, the CPU starts executing the software from address
0 in page 0. In this case, the P flag is “1.”
(2) Cold start condition
The CPU starts executing the software from address 0 in page
0 when any of the following conditions is satisfied .
• reset by power-on reset circuit is performed
• reset by watchdog timer is performed
• reset by voltage drop detection circuit is performed
In this case, the P flag is “0.”
(3) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
Table 7 Functions and states retained at RAM back-up
Function
RAM back-up
Program counter (PC), registers A, B,
✕
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
O
Port CARR
✕
Ports D0–D7
O
Ports E0, E1
O
Port G
O
Timer control registers V1, V2
✕
Pull-down control registers PU0, PU1
O
Logic operation selection register LO
✕
Timer 1 function, Timer 2 function
✕
Timer underflow flags (T1F, T2F)
✕
Watchdog timer (WDT)
✕
Watchdog timer flags (WDF1, WDF2)
✕
MostsignificantROMcodereferenceenableflag(URS)
✕
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to “112” at RAM back-up.
Reset
(Stabilizing time a )
A
POF instruction
is executed
f(XIN) oscillation
Return input
(Stabilizing time a )
B
f(XIN) stop
(RAM back-up
mode)
Stabilizing time a : Microcomputer starts its operation after f(XIN) is counted to16384 times.
Fig. 23 State transition
POF instruction
Power down flag P
SQ
Reset input
R
● Set source
● Clear source
POF instruction is executed
Reset input
Fig. 24 Set source and clear source of the P flag
Software start
P = “1” Yes
?
No
Cold start
Warm start
Fig. 25 Start condition identified example using the SNZP
instruction
Rev.1.33 Mar 18, 2004 page 19 of 67
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