M34282M2-XXXGP View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

M34282M2-XXXGP

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Renesas Electronics 

4282 Group

BML p, a (Branch and Mark Long to address a in page p)

Instrunction D8

D0

code

0 0 1 1 1 p3 p2 p1 p0

2

Number of Number of Flag CY

07p

words

cycles

16

2

2

–

Skip condition

–

1 0 a6 a5 a4 a3 a2 a1 a0 2

1 a a 16

Grouping: Subroutine call operation

Operation:

(SK(SP)) ← (PC)

(SP) ← (SP) + 1

(PCH) ← p

(PCL) ← a6–a0

Description: Call the subroutine : Calls the subroutine at

address a in page p.

Note:

p is 0 to 7 for M34282M1,

p is 0 to 15 for M34282M2/E2.

BMLA p, a (Branch and Mark Long to address a in page p)

Instrunction D8

D0

code

001010000

2

Number of Number of Flag CY

050

words

cycles

16

2

2

–

Skip condition

–

Operation:

1 0 a6 a5 a4 p3 p2 p1 p0 2

(SK(SP)) ← (PC)

(SP) ← (SP) + 1

(PCH) ← p

(PCL) ← (a6–a4, A3–A0)

1 a p 16 Grouping: Subroutine call operation

Description: Call the subroutine : Calls the subroutine at

address (a6 a5 a4 A3 A2 A1 A0) determined

by replacing the low-order 4 bits of address

a in page p with register A.

Note:

p is 0 to 7 for M34282M1,

p is 0 to 15 for M34282M2/E2.

CCK (Change system Clock to f(XIN))

Instrunction D8

D0

code

001011001

2

Operation: Change to STCK = f(XIN)

Number of Number of Flag CY

059

words

cycles

16

1

1

–

Skip condition

–

Grouping: Other operation

Description: Changes system clock (STCK) from f(XIN)/8

to f(XIN). Execute this instruction at address

0 in page 0.

CLD (CLear port D)

Instrunction D8

D0

code

000010001

2

Operation: (D) ← 1

Number of Number of Flag CY

011

words

cycles

16

1

1

–

Skip condition

–

Grouping: Input/Output operation

Description: Clears (0) to port D (high-impedance state).

Rev.1.33 Mar 18, 2004 page 29 of 67

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