M34282M1 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
M34282M1 Datasheet PDF : 69 Pages
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4282 Group
(4) Program
Input command code 2516 in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
and pull the PGM pin to “L.” When this is done, the program
data is programmed to the specified address.
SCLK
SDA
PGM
tCH
tCH
tCH
tCH
A0
A7
A8 A9 A10
D0
D7
D8
10 100100
00000
00 000 00
Commanf code input (2516)Program address input (L) Program address input (H) Program data input (L) Program data input (H)
tCP
tWP
Program
Fig. 32 Timing at programming
(5) Program verify
Input command code 3516 in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
and pull the PGM pin to “L.” When this is done, the program
data is programmed to the specified address. Then, when the
PGM pin is pulled to “L” again after it is released back to “H,”
the address programmed with the program command is read
and verified and stored into the internal data latch. When the
PGM pin is released back to “H” and serial clock is input to the
SCLK pin, the verify data that has been stored into the data
latch is serially output from the SDA pin.
tCH
tCH
tCH
tCH
SCLK
SDA
1 0 101 100
Command code input (3516)
A0
A7
A8 A9A10
00000
Program address input (L) Program address input (H)
D0
D7
Program data input (L)
D8
00 00000
Program data input (H)
tCP
tWP
PGM
SCLK
SDA
tCH
D0
D7
Verify data output (L)
tCR tWR tRC
D8
0000 000
Verify data output (H)
Program
PGM
Verify
Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is
placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit).
Fig. 33 Timing at program verifying
Rev.1.33 Mar 18, 2004 page 63 of 67
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