M38B78FDH-XXXXFP View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part Name

Description

Manufacturer

M38B78FDH-XXXXFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

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MITSUBISHI MICROCOMPUTERS

38B7 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS

[Direction Registers] PiD

The 38B7 group has 75 programmable I/O pins arranged in ten in-

dividual I/O ports (P1, P3, P4, P5, P6, P7, P8, P9, PA and PB).

The I/O ports have direction registers which determine the input/

output direction of each individual pin. Each bit in a direction reg-

ister corresponds to one pin, and each pin can be set to be input

port or output port. When “0” is written to the bit corresponding to

a pin, that pin becomes an input pin. When “1” is written to that

pin, that pin becomes an output pin. If data is read from a pin set

to output, the value of the port output latch is read, not the value of

the pin itself. Pins set to input (the bit corresponding to that pin

must be set to “0”) are floating and the value of that pin can be

read. If a pin set to input is written to, only the port output latch is

written to and the pin remains floating.

[High-Breakdown-Voltage Output Ports]

The 38B7 group has seven ports with high-breakdown-voltage

pins (por ts P0 to P5 and P60–P63). The high-breakdown-voltage

ports have P-channel open-drain output with Vcc – 45 V of break-

down voltage. Each pin in ports P0 to P3 has an internal pull-down

resistor connected to VEE. At reset, the P-channel output transis-

tor of each port latch is turned off, so that it goes to VEE level (“L”)

by the pull-down resistor.

Writing “1” (weak drivability) to bit 7 of the FLDC mode register

(address 0EF416) shows the rising transition of the output transis-

tors for reducing transient noise. At reset, bit 7 of the FLDC mode

register is set to “0” (strong drivability).

[Pull-up Control Register] PULL

Ports P64–P67, P7, P80–P83, P9, PA and PB have built-in pro-

grammable pull-up resistors. The pull-up resistors are valid only in

the case that the each control bit is set to “1” and the correspond-

ing port direction registers are set to input mode.

b7

b0

b7

Pull-up control register 1

(PULL1 : address 0EF016)

P64, P65 pull-up control bit

P66, P67 pull-up control bit

P70, P71 pull-up control bit

P72, P73 pull-up control bit

P74, P75 pull-up control bit

0: No pull-up

1: Pull-up

P76, P77 pull-up control bit

Not used (returns “0” when read)

(Do not write “1”.)

b7

b0

Pull-up control register 3

(PULL3 : address 0EEF16)

PA0, PA1 pull-up control bit

PA2, PA3 pull-up control bit

PA4, PA5 pull-up control bit

PA6, PA7 pull-up control bit

PB0, PB1 pull-up control bit

0: No pull-up

1: Pull-up

PB2, PB3 pull-up control bit

PB4, PB5 pull-up control bit

PB6 pull-up control bit

Fig. 10 Structure of pull-up control registers (PULL1, PULL2 and PULL3)

b0

Pull-up control register 2

(PULL2 : address 0EF116)

P80, P81 pull-up control bit

P82, P83 pull-up control bit

Not used (returns “0” when read)

(Do not write “1”.)

P90, P91 pull-up control bit

P92, P93 pull-up control bit

P94, P95 pull-up control bit

P96, P97 pull-up control bit

Not used (returns “0” when read)

(Do not write “1”.)

0: No pull-up

1: Pull-up

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