M38B78FBFP View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
Manufacturer
M38B78FBFP Datasheet PDF : 109 Pages
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MITSUBISHI MICROCOMPUTERS
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 1 Pin description (1)
Pin
VCC, VSS
CNVSS
Name
Power source
CNVSS
VEE
Pull-down
power source
Function
• Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS.
• Connect to VSS.
• VPP power input pin in flash memory mode.
• Apply voltage supplied to pull-down resistors of ports P0, P1, P2 and P3.
Function except a port function
VREF
AVSS
______
RESET
XIN
Reference voltage
Analog power
source
Reset input
Clock input
XOUT
Clock output
P00/FLD8– Output port P0
P07/FLD15
P10/FLD16– I/O port P1
P17/FLD23
• Reference voltage input pin for A-D converter.
• Analog power source input pin for A-D converter.
• Connect to VSS.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
• 8-bit output port.
• FLD automatic display
• High-breakdown-voltage P-channel open-drain output structure.
pins
• A pull-down resistor is built in between port P0 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port.
• FLD automatic display
• I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
P20/FLD0– Output port P2
P27/FLD7
P30/FLD24– I/O port P3
P37/FLD31
P40/FLD32– I/O port P4
P47/FLD39
P50/FLD40– I/O port P5
P57/FLD47
P60/FLD48– I/O port P6
P63/FLD51
• A pull-down resistor is built in between port P1 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit output port with the same function as port P0.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P2 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P3 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P4 and the VEE pin.
• 8-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P5 and the VEE pin.
• 4-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P6 and the VEE pin.
• FLD automatic display
pins
• FLD automatic display
pins
• FLD automatic display
pins
• FLD automatic display
pins
• FLD automatic display
pins
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