MC13158FTB View Datasheet(PDF) - LANSDALE Semiconductor Inc.

Part Name

Description

Manufacturer

MC13158FTB

Wideband FM IF Subsystem For Dect and Digital Applications

LANSDALE Semiconductor Inc. 

ML13158

LANSDALE Semiconductor, Inc.

Legacy Applications Information

EXAMPLE:

Let the external Cext = 139 pF. (The miminum value here should

be much greater than the internal device and PCB parasitic capaci-

tance, Cint = 3.0 pF.). Thus, Cp = Cint + Cext = 142 pF.

Rewrite equation (2) and solve for L

L = (0.159)2/(Cpfc2)

L = 1.56 µH; Thus, a standard value is chosen:

L = 1.56 µH (tunable shielded inductor)

The value of the total damping resistor to obtain the required

loaded Q of 18 can be calculated by rearranging equation (1):

RT = Q(2πfl)

RT = 18(2π)(10.7)(1.5) = 1815Ω

The internal resistance, Rint at the quadrature tank Pin 13 is

approximately 13 kΩ and is considered in determining the external

resistance, Rext which is calculated from

Rext = ((RT)(Rint))/(Rint – RT)

Rext = 2110; Thus choose the standard value

Rext = 2.2 kΩ

It is important to set the DC level of the detector output at Pin 17 to

center the peak to peak swing of the recovered signal. In the equiv-

alent internal circuit shown in the Pin Function Description, the ref-

erence voltage at the positive terminal of the inverting, op amp

buffer amplifier is set at 1.0 VBE. The detector DC level, V17 is

determined by the following equation:

V17 = [((R15/R17) + 1 )/(R15/R17)] VBE

Thus for a 1:1 ratio of R15/R17, V17 = 2.0 VBE = 1.4 Vdc.

Similarly for a 2:1, V17 = 1.5 VBE = 1.05 Vdc; and for 3:1, V17 =

1.33 VBE = 0.93 Vdc.

Figure 19 shows the detector “S–Curves”, in which the resistor

ratio is varied while maintaining a constant gain (R17 is held at 62

kΩ). R15 is 62 kΩ for a 1:1 ratio; while R15 = 120 kΩ and 180 kΩ

to produce the 2:1 and 3:1 ratio. The IF signal into the detector is

swept ± 500 KHz about the 10.7 MHz, IF center frequency. The

resulting curve show how the resistor ratio and the supply voltage

effects the symmetry of the “S–curve” (Figure 21 Test Setup). For

the 3:1 and 2:1 ratio, symmetry is maintained with VS from 2.0 to

5.0 Vdc; however, for the 1:1 ratio, symmetry is lost at 2.0 Vdc.

DATA SLICER CIRCUIT

C20 at the input of the data slicer is chosen to maintian a time con-

stant long enought to hold the charge on the capacitor for the

longest strings of bits at the same polarity. For a data rate of 576

kHz a bit stream of 15 bits at the same plarity would equate to an

apparent data rate of approximately 77 kbps or 38 kHz. The time

constant would be approximately 26 µs. The following expression

equates the time constant t, to the external components;

t = 2π (R18)(C20)

Solve for C20:

C20 = t/2π (R18)

where the effective resistance R18 is a complex function of the

demodulator feedback resistance and data slicer input circuit. In the

data input network the back to back diodes form a charge and dis-

charge path for the capacitor at Pin 20; however, the diodes create a

non–linear response. This resistance is loaded by the ß, beta of the

detector output transistor; beta = 100 is a typical value (see Figure

21). Thus, the apparent value of the resitance at Pin 18 (DS IN1) is

approximately equal to:

R18 ~ R17/100

where R17 is 82 kΩ, the feedback resistor from Pin 17 to 15.

Therefore, substituting for R18 and solving for C20:

C20 = 15.9 (t)/R17 = 5.04 nF

The closest standard value is 4.7 nF.

Page 17 of 23

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